1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <pmic_wrap_init.h> 8*91f16700Schasinglulu #include <pmic.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu void bcpu_enable(uint32_t en) 11*91f16700Schasinglulu { 12*91f16700Schasinglulu pwrap_write(PMIC_VPROC11_OP_EN, 0x1); 13*91f16700Schasinglulu if (en) 14*91f16700Schasinglulu pwrap_write(PMIC_VPROC11_CON0, 1); 15*91f16700Schasinglulu else 16*91f16700Schasinglulu pwrap_write(PMIC_VPROC11_CON0, 0); 17*91f16700Schasinglulu } 18*91f16700Schasinglulu 19*91f16700Schasinglulu void bcpu_sram_enable(uint32_t en) 20*91f16700Schasinglulu { 21*91f16700Schasinglulu pwrap_write(PMIC_VSRAM_PROC11_OP_EN, 0x1); 22*91f16700Schasinglulu if (en) 23*91f16700Schasinglulu pwrap_write(PMIC_VSRAM_PROC11_CON0, 1); 24*91f16700Schasinglulu else 25*91f16700Schasinglulu pwrap_write(PMIC_VSRAM_PROC11_CON0, 0); 26*91f16700Schasinglulu } 27*91f16700Schasinglulu 28*91f16700Schasinglulu void wk_pmic_enable_sdn_delay(void) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu uint32_t con; 31*91f16700Schasinglulu 32*91f16700Schasinglulu pwrap_write(PMIC_TMA_KEY, 0x9CA7); 33*91f16700Schasinglulu pwrap_read(PMIC_PSEQ_ELR11, &con); 34*91f16700Schasinglulu con &= ~PMIC_RG_SDN_DLY_ENB; 35*91f16700Schasinglulu pwrap_write(PMIC_PSEQ_ELR11, con); 36*91f16700Schasinglulu pwrap_write(PMIC_TMA_KEY, 0); 37*91f16700Schasinglulu } 38*91f16700Schasinglulu 39*91f16700Schasinglulu void pmic_power_off(void) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu pwrap_write(PMIC_PWRHOLD, 0x0); 42*91f16700Schasinglulu } 43