xref: /arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcdi/mtk_mcdi.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef __MTK_MCDI_H__
8*91f16700Schasinglulu #define __MTK_MCDI_H__
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <stdbool.h>
11*91f16700Schasinglulu 
12*91f16700Schasinglulu void sspm_set_bootaddr(uint32_t bootaddr);
13*91f16700Schasinglulu void sspm_standbywfi_irq_enable(uint32_t cpu_idx);
14*91f16700Schasinglulu void sspm_cluster_pwr_off_notify(uint32_t cluster);
15*91f16700Schasinglulu void sspm_cluster_pwr_on_notify(uint32_t cluster);
16*91f16700Schasinglulu 
17*91f16700Schasinglulu uint32_t mcdi_avail_cpu_mask_read(void);
18*91f16700Schasinglulu uint32_t mcdi_avail_cpu_mask_write(uint32_t mask);
19*91f16700Schasinglulu uint32_t mcdi_avail_cpu_mask_set(uint32_t mask);
20*91f16700Schasinglulu uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask);
21*91f16700Schasinglulu uint32_t mcdi_cpu_cluster_pwr_stat_read(void);
22*91f16700Schasinglulu 
23*91f16700Schasinglulu void mcdi_pause(void);
24*91f16700Schasinglulu void mcdi_unpause(void);
25*91f16700Schasinglulu void mcdi_pause_set(int cluster, int cpu_idx, bool on);
26*91f16700Schasinglulu void mcdi_pause_clr(int cluster, int cpu_idx, bool on);
27*91f16700Schasinglulu void mcdi_hotplug_set(int cluster, int cpu_idx, bool on);
28*91f16700Schasinglulu void mcdi_hotplug_clr(int cluster, int cpu_idx, bool on);
29*91f16700Schasinglulu void mcdi_hotplug_wait_ack(int cluster, int cpu_idx, bool on);
30*91f16700Schasinglulu 
31*91f16700Schasinglulu bool check_mcdi_ctl_stat(void);
32*91f16700Schasinglulu void mcdi_init(void);
33*91f16700Schasinglulu 
34*91f16700Schasinglulu #endif /* __MTK_MCDI_H__ */
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