xref: /arm-trusted-firmware/plat/mediatek/mt8183/drivers/emi_mpu/emi_mpu.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef __EMI_MPU_H
8*91f16700Schasinglulu #define __EMI_MPU_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <platform_def.h>
11*91f16700Schasinglulu 
12*91f16700Schasinglulu #define EMI_MPUP		(EMI_BASE + 0x01D8)
13*91f16700Schasinglulu #define EMI_MPUQ		(EMI_BASE + 0x01E0)
14*91f16700Schasinglulu #define EMI_MPUR		(EMI_BASE + 0x01E8)
15*91f16700Schasinglulu #define EMI_MPUS		(EMI_BASE + 0x01F0)
16*91f16700Schasinglulu #define EMI_MPUT		(EMI_BASE + 0x01F8)
17*91f16700Schasinglulu #define EMI_MPUY		(EMI_BASE + 0x0220)
18*91f16700Schasinglulu #define EMI_MPU_CTRL	(EMI_MPU_BASE + 0x0000)
19*91f16700Schasinglulu #define EMI_MPUD0_ST	(EMI_BASE + 0x0160)
20*91f16700Schasinglulu #define EMI_MPUD1_ST	(EMI_BASE + 0x0164)
21*91f16700Schasinglulu #define EMI_MPUD2_ST	(EMI_BASE + 0x0168)
22*91f16700Schasinglulu #define EMI_MPUD3_ST	(EMI_BASE + 0x016C)
23*91f16700Schasinglulu #define EMI_MPUD0_ST2	(EMI_BASE + 0x0200)
24*91f16700Schasinglulu #define EMI_MPUD1_ST2	(EMI_BASE + 0x0204)
25*91f16700Schasinglulu #define EMI_MPUD2_ST2	(EMI_BASE + 0x0208)
26*91f16700Schasinglulu #define EMI_MPUD3_ST2	(EMI_BASE + 0x020C)
27*91f16700Schasinglulu 
28*91f16700Schasinglulu #define EMI_PHY_OFFSET	(0x40000000UL)
29*91f16700Schasinglulu #define EIGHT_DOMAIN
30*91f16700Schasinglulu 
31*91f16700Schasinglulu #define NO_PROTECTION	(0)
32*91f16700Schasinglulu #define SEC_RW			(1)
33*91f16700Schasinglulu #define SEC_RW_NSEC_R	(2)
34*91f16700Schasinglulu #define SEC_RW_NSEC_W	(3)
35*91f16700Schasinglulu #define SEC_R_NSEC_R	(4)
36*91f16700Schasinglulu #define FORBIDDEN		(5)
37*91f16700Schasinglulu #define SEC_R_NSEC_RW	(6)
38*91f16700Schasinglulu 
39*91f16700Schasinglulu #define SECURE_OS_MPU_REGION_ID	(0)
40*91f16700Schasinglulu #define ATF_MPU_REGION_ID		(1)
41*91f16700Schasinglulu 
42*91f16700Schasinglulu #ifdef EIGHT_DOMAIN
43*91f16700Schasinglulu #define SET_ACCESS_PERMISSON(d7, d6, d5, d4, d3, d2, d1, d0) \
44*91f16700Schasinglulu 	(((d7) << 21) | ((d6) << 18) | ((d5) << 15) | ((d4) << 12) \
45*91f16700Schasinglulu 	| ((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
46*91f16700Schasinglulu #else
47*91f16700Schasinglulu #define SET_ACCESS_PERMISSON(d3, d2, d1, d0) \
48*91f16700Schasinglulu 	(((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
49*91f16700Schasinglulu #endif
50*91f16700Schasinglulu 
51*91f16700Schasinglulu //#define EMI_MPU_BASE                (0x1020E000U)
52*91f16700Schasinglulu 
53*91f16700Schasinglulu #define EMI_MPU_SA0                 (EMI_MPU_BASE + 0x100)
54*91f16700Schasinglulu #define EMI_MPU_SA1                 (EMI_MPU_BASE + 0x104)
55*91f16700Schasinglulu #define EMI_MPU_SA2                 (EMI_MPU_BASE + 0x108)
56*91f16700Schasinglulu #define EMI_MPU_SA3                 (EMI_MPU_BASE + 0x10C)
57*91f16700Schasinglulu #define EMI_MPU_SA4                 (EMI_MPU_BASE + 0x110)
58*91f16700Schasinglulu #define EMI_MPU_SA5                 (EMI_MPU_BASE + 0x114)
59*91f16700Schasinglulu #define EMI_MPU_SA6                 (EMI_MPU_BASE + 0x118)
60*91f16700Schasinglulu #define EMI_MPU_SA7                 (EMI_MPU_BASE + 0x11C)
61*91f16700Schasinglulu 
62*91f16700Schasinglulu #define EMI_MPU_EA0                 (EMI_MPU_BASE + 0x200)
63*91f16700Schasinglulu #define EMI_MPU_EA1                 (EMI_MPU_BASE + 0x204)
64*91f16700Schasinglulu #define EMI_MPU_EA2                 (EMI_MPU_BASE + 0x208)
65*91f16700Schasinglulu #define EMI_MPU_EA3                 (EMI_MPU_BASE + 0x20C)
66*91f16700Schasinglulu #define EMI_MPU_EA4                 (EMI_MPU_BASE + 0x210)
67*91f16700Schasinglulu #define EMI_MPU_EA5                 (EMI_MPU_BASE + 0x214)
68*91f16700Schasinglulu #define EMI_MPU_EA6                 (EMI_MPU_BASE + 0x218)
69*91f16700Schasinglulu #define EMI_MPU_EA7                 (EMI_MPU_BASE + 0x21C)
70*91f16700Schasinglulu 
71*91f16700Schasinglulu #define EMI_MPU_APC0                (EMI_MPU_BASE + 0x300)
72*91f16700Schasinglulu #define EMI_MPU_APC1                (EMI_MPU_BASE + 0x304)
73*91f16700Schasinglulu #define EMI_MPU_APC2                (EMI_MPU_BASE + 0x308)
74*91f16700Schasinglulu #define EMI_MPU_APC3                (EMI_MPU_BASE + 0x30C)
75*91f16700Schasinglulu #define EMI_MPU_APC4                (EMI_MPU_BASE + 0x310)
76*91f16700Schasinglulu #define EMI_MPU_APC5                (EMI_MPU_BASE + 0x314)
77*91f16700Schasinglulu #define EMI_MPU_APC6                (EMI_MPU_BASE + 0x318)
78*91f16700Schasinglulu #define EMI_MPU_APC7                (EMI_MPU_BASE + 0x31C)
79*91f16700Schasinglulu 
80*91f16700Schasinglulu #define EMI_MPU_CTRL_D0             (EMI_MPU_BASE + 0x800)
81*91f16700Schasinglulu #define EMI_MPU_CTRL_D1             (EMI_MPU_BASE + 0x804)
82*91f16700Schasinglulu #define EMI_MPU_CTRL_D2             (EMI_MPU_BASE + 0x808)
83*91f16700Schasinglulu #define EMI_MPU_CTRL_D3             (EMI_MPU_BASE + 0x80C)
84*91f16700Schasinglulu #define EMI_MPU_CTRL_D4             (EMI_MPU_BASE + 0x810)
85*91f16700Schasinglulu #define EMI_MPU_CTRL_D5             (EMI_MPU_BASE + 0x814)
86*91f16700Schasinglulu #define EMI_MPU_CTRL_D6             (EMI_MPU_BASE + 0x818)
87*91f16700Schasinglulu #define EMI_MPU_CTRL_D7             (EMI_MPU_BASE + 0x81C)
88*91f16700Schasinglulu 
89*91f16700Schasinglulu #define EMI_MPU_MASK_D0             (EMI_MPU_BASE + 0x900)
90*91f16700Schasinglulu #define EMI_MPU_MASK_D1             (EMI_MPU_BASE + 0x904)
91*91f16700Schasinglulu #define EMI_MPU_MASK_D2             (EMI_MPU_BASE + 0x908)
92*91f16700Schasinglulu #define EMI_MPU_MASK_D3             (EMI_MPU_BASE + 0x90C)
93*91f16700Schasinglulu #define EMI_MPU_MASK_D4             (EMI_MPU_BASE + 0x910)
94*91f16700Schasinglulu #define EMI_MPU_MASK_D5             (EMI_MPU_BASE + 0x914)
95*91f16700Schasinglulu #define EMI_MPU_MASK_D6             (EMI_MPU_BASE + 0x918)
96*91f16700Schasinglulu #define EMI_MPU_MASK_D7             (EMI_MPU_BASE + 0x91C)
97*91f16700Schasinglulu 
98*91f16700Schasinglulu int emi_mpu_set_region_protection(
99*91f16700Schasinglulu 	unsigned long start, unsigned long end,
100*91f16700Schasinglulu 	int region,
101*91f16700Schasinglulu 	unsigned int access_permission);
102*91f16700Schasinglulu 
103*91f16700Schasinglulu void dump_emi_mpu_regions(void);
104*91f16700Schasinglulu void emi_mpu_init(void);
105*91f16700Schasinglulu 
106*91f16700Schasinglulu #endif  /* __EMI_MPU_H */
107