1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <mcucfg.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu void disable_scu(unsigned long mpidr) 13*91f16700Schasinglulu { 14*91f16700Schasinglulu if (mpidr & MPIDR_CLUSTER_MASK) 15*91f16700Schasinglulu mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 16*91f16700Schasinglulu MP1_ACINACTM); 17*91f16700Schasinglulu else 18*91f16700Schasinglulu mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 19*91f16700Schasinglulu MP0_ACINACTM); 20*91f16700Schasinglulu } 21*91f16700Schasinglulu 22*91f16700Schasinglulu void enable_scu(unsigned long mpidr) 23*91f16700Schasinglulu { 24*91f16700Schasinglulu if (mpidr & MPIDR_CLUSTER_MASK) 25*91f16700Schasinglulu mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, 26*91f16700Schasinglulu MP1_ACINACTM); 27*91f16700Schasinglulu else 28*91f16700Schasinglulu mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, 29*91f16700Schasinglulu MP0_ACINACTM); 30*91f16700Schasinglulu } 31