1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch.h> 10*91f16700Schasinglulu #include <lib/psci/psci.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu const unsigned char mtk_power_domain_tree_desc[] = { 13*91f16700Schasinglulu /* No of root nodes */ 14*91f16700Schasinglulu PLATFORM_SYSTEM_COUNT, 15*91f16700Schasinglulu /* No of children for the root node */ 16*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT, 17*91f16700Schasinglulu /* No of children for the first cluster node */ 18*91f16700Schasinglulu PLATFORM_CLUSTER0_CORE_COUNT, 19*91f16700Schasinglulu /* No of children for the second cluster node */ 20*91f16700Schasinglulu PLATFORM_CLUSTER1_CORE_COUNT 21*91f16700Schasinglulu }; 22*91f16700Schasinglulu 23*91f16700Schasinglulu /******************************************************************************* 24*91f16700Schasinglulu * This function returns the MT8173 default topology tree information. 25*91f16700Schasinglulu ******************************************************************************/ 26*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu return mtk_power_domain_tree_desc; 29*91f16700Schasinglulu } 30*91f16700Schasinglulu 31*91f16700Schasinglulu /******************************************************************************* 32*91f16700Schasinglulu * This function implements a part of the critical interface between the psci 33*91f16700Schasinglulu * generic layer and the platform that allows the former to query the platform 34*91f16700Schasinglulu * to convert an MPIDR to a unique linear index. An error code (-1) is returned 35*91f16700Schasinglulu * in case the MPIDR is invalid. 36*91f16700Schasinglulu ******************************************************************************/ 37*91f16700Schasinglulu int plat_core_pos_by_mpidr(u_register_t mpidr) 38*91f16700Schasinglulu { 39*91f16700Schasinglulu unsigned int cluster_id, cpu_id; 40*91f16700Schasinglulu 41*91f16700Schasinglulu mpidr &= MPIDR_AFFINITY_MASK; 42*91f16700Schasinglulu 43*91f16700Schasinglulu if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) 44*91f16700Schasinglulu return -1; 45*91f16700Schasinglulu 46*91f16700Schasinglulu cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 47*91f16700Schasinglulu cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 48*91f16700Schasinglulu 49*91f16700Schasinglulu if (cluster_id >= PLATFORM_CLUSTER_COUNT) 50*91f16700Schasinglulu return -1; 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* 53*91f16700Schasinglulu * Validate cpu_id by checking whether it represents a CPU in 54*91f16700Schasinglulu * one of the two clusters present on the platform. 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 57*91f16700Schasinglulu return -1; 58*91f16700Schasinglulu 59*91f16700Schasinglulu return (cpu_id + (cluster_id * 4)); 60*91f16700Schasinglulu } 61