1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef RTC_H 8*91f16700Schasinglulu #define RTC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* RTC registers */ 11*91f16700Schasinglulu enum { 12*91f16700Schasinglulu RTC_BBPU = 0xE000, 13*91f16700Schasinglulu RTC_IRQ_STA = 0xE002, 14*91f16700Schasinglulu RTC_IRQ_EN = 0xE004, 15*91f16700Schasinglulu RTC_CII_EN = 0xE006 16*91f16700Schasinglulu }; 17*91f16700Schasinglulu 18*91f16700Schasinglulu enum { 19*91f16700Schasinglulu RTC_OSC32CON = 0xE026, 20*91f16700Schasinglulu RTC_CON = 0xE03E, 21*91f16700Schasinglulu RTC_WRTGR = 0xE03C 22*91f16700Schasinglulu }; 23*91f16700Schasinglulu 24*91f16700Schasinglulu enum { 25*91f16700Schasinglulu RTC_PDN1 = 0xE02C, 26*91f16700Schasinglulu RTC_PDN2 = 0xE02E, 27*91f16700Schasinglulu RTC_SPAR0 = 0xE030, 28*91f16700Schasinglulu RTC_SPAR1 = 0xE032, 29*91f16700Schasinglulu RTC_PROT = 0xE036, 30*91f16700Schasinglulu RTC_DIFF = 0xE038, 31*91f16700Schasinglulu RTC_CALI = 0xE03A 32*91f16700Schasinglulu }; 33*91f16700Schasinglulu 34*91f16700Schasinglulu enum { 35*91f16700Schasinglulu RTC_PROT_UNLOCK1 = 0x586A, 36*91f16700Schasinglulu RTC_PROT_UNLOCK2 = 0x9136 37*91f16700Schasinglulu }; 38*91f16700Schasinglulu 39*91f16700Schasinglulu enum { 40*91f16700Schasinglulu RTC_BBPU_PWREN = 1U << 0, 41*91f16700Schasinglulu RTC_BBPU_BBPU = 1U << 2, 42*91f16700Schasinglulu RTC_BBPU_AUTO = 1U << 3, 43*91f16700Schasinglulu RTC_BBPU_CLRPKY = 1U << 4, 44*91f16700Schasinglulu RTC_BBPU_RELOAD = 1U << 5, 45*91f16700Schasinglulu RTC_BBPU_CBUSY = 1U << 6 46*91f16700Schasinglulu }; 47*91f16700Schasinglulu 48*91f16700Schasinglulu enum { 49*91f16700Schasinglulu RTC_BBPU_KEY = 0x43 << 8 50*91f16700Schasinglulu }; 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* external API */ 53*91f16700Schasinglulu uint16_t RTC_Read(uint32_t addr); 54*91f16700Schasinglulu void RTC_Write(uint32_t addr, uint16_t data); 55*91f16700Schasinglulu int32_t rtc_busy_wait(void); 56*91f16700Schasinglulu int32_t RTC_Write_Trigger(void); 57*91f16700Schasinglulu int32_t Writeif_unlock(void); 58*91f16700Schasinglulu void rtc_bbpu_power_down(void); 59*91f16700Schasinglulu 60*91f16700Schasinglulu #endif /* RTC_H */ 61