1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <arch.h> 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <mt8173_def.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 11*91f16700Schasinglulu .globl plat_report_exception 12*91f16700Schasinglulu .globl platform_is_primary_cpu 13*91f16700Schasinglulu .globl plat_my_core_pos 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* ----------------------------------------------------- 16*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 17*91f16700Schasinglulu * 18*91f16700Schasinglulu * This function performs any platform specific actions 19*91f16700Schasinglulu * needed for a secondary cpu after a cold reset e.g 20*91f16700Schasinglulu * mark the cpu's presence, mechanism to place it in a 21*91f16700Schasinglulu * holding pen etc. 22*91f16700Schasinglulu * ----------------------------------------------------- 23*91f16700Schasinglulu */ 24*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 25*91f16700Schasinglulu /* MT8173 Oak does not do cold boot for secondary CPU */ 26*91f16700Schasinglulucb_panic: 27*91f16700Schasinglulu b cb_panic 28*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 29*91f16700Schasinglulu 30*91f16700Schasinglulufunc platform_is_primary_cpu 31*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 32*91f16700Schasinglulu cmp x0, #MT8173_PRIMARY_CPU 33*91f16700Schasinglulu cset x0, eq 34*91f16700Schasinglulu ret 35*91f16700Schasingluluendfunc platform_is_primary_cpu 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* ----------------------------------------------------- 38*91f16700Schasinglulu * unsigned int plat_my_core_pos(void); 39*91f16700Schasinglulu * 40*91f16700Schasinglulu * result: CorePos = CoreId + (ClusterId << 2) 41*91f16700Schasinglulu * ----------------------------------------------------- 42*91f16700Schasinglulu */ 43*91f16700Schasinglulufunc plat_my_core_pos 44*91f16700Schasinglulu mrs x0, mpidr_el1 45*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 46*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 47*91f16700Schasinglulu add x0, x1, x0, LSR #6 48*91f16700Schasinglulu ret 49*91f16700Schasingluluendfunc plat_my_core_pos 50