1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, Mediatek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef ARCH_DEF_H 8*91f16700Schasinglulu #define ARCH_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* Topology constants */ 11*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL (2) 12*91f16700Schasinglulu #define PLAT_MAX_RET_STATE (1) 13*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE (2) 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLATFORM_SYSTEM_COUNT (1) 16*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT (1) 17*91f16700Schasinglulu #define PLATFORM_CLUSTER0_CORE_COUNT (8) 18*91f16700Schasinglulu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 19*91f16700Schasinglulu #define PLATFORM_MAX_CPUS_PER_CLUSTER (8) 20*91f16700Schasinglulu #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 21*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT + \ 22*91f16700Schasinglulu PLATFORM_CORE_COUNT) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /******************************************************************************* 25*91f16700Schasinglulu * Declarations and constants to access the mailboxes safely. Each mailbox is 26*91f16700Schasinglulu * aligned on the biggest cache line size in the platform. This is known only 27*91f16700Schasinglulu * to the platform as it might have a combination of integrated and external 28*91f16700Schasinglulu * caches. Such alignment ensures that two maiboxes do not sit on the same cache 29*91f16700Schasinglulu * line at any cache level. They could belong to different cpus/clusters & 30*91f16700Schasinglulu * get written while being protected by different locks causing corruption of 31*91f16700Schasinglulu * a valid mailbox address. 32*91f16700Schasinglulu ******************************************************************************/ 33*91f16700Schasinglulu /* Cachline size */ 34*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT (6) 35*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 36*91f16700Schasinglulu 37*91f16700Schasinglulu #endif /* ARCH_DEF_H */ 38*91f16700Schasinglulu 39