1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2022, Mediatek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <cpu_macros.S> 11*91f16700Schasinglulu#if CONFIG_MTK_MCUSYS 12*91f16700Schasinglulu#include <mcucfg.h> 13*91f16700Schasinglulu#endif 14*91f16700Schasinglulu#include <platform_def.h> 15*91f16700Schasinglulu /* 16*91f16700Schasinglulu * Declare as weak function so that can be 17*91f16700Schasinglulu * overwritten by platform helpers 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu .weak platform_mem_init 20*91f16700Schasinglulu .weak plat_core_pos_by_mpidr 21*91f16700Schasinglulu .weak plat_my_core_pos 22*91f16700Schasinglulu .weak plat_mediatek_calc_core_pos 23*91f16700Schasinglulu .global plat_mpidr_by_core_pos 24*91f16700Schasinglulu .global plat_reset_handler 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* ----------------------------------------------------- 27*91f16700Schasinglulu * unsigned long plat_mpidr_by_core_pos(uint32_t cpuid) 28*91f16700Schasinglulu * This function calcuate mpidr by cpu pos if cpu 29*91f16700Schasinglulu * topology is linear. 30*91f16700Schasinglulu * 31*91f16700Schasinglulu * Clobbers: x0-x1 32*91f16700Schasinglulu * ----------------------------------------------------- 33*91f16700Schasinglulu */ 34*91f16700Schasinglulufunc plat_mpidr_by_core_pos 35*91f16700Schasinglulu lsl x0, x0, #MPIDR_AFF1_SHIFT 36*91f16700Schasinglulu mrs x1, mpidr_el1 37*91f16700Schasinglulu and x1, x1, #MPIDR_MT_MASK 38*91f16700Schasinglulu orr x0, x0, x1 39*91f16700Schasinglulu ret 40*91f16700Schasingluluendfunc plat_mpidr_by_core_pos 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* ----------------------------------------------------- 43*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 44*91f16700Schasinglulu * This function uses the plat_arm_calc_core_pos() 45*91f16700Schasinglulu * definition to get the index of the calling CPU. 46*91f16700Schasinglulu * ----------------------------------------------------- 47*91f16700Schasinglulu */ 48*91f16700Schasinglulufunc plat_my_core_pos 49*91f16700Schasinglulu mrs x0, mpidr_el1 50*91f16700Schasinglulu b plat_mediatek_calc_core_pos 51*91f16700Schasingluluendfunc plat_my_core_pos 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* ----------------------------------------------------- 54*91f16700Schasinglulu * int plat_mediatek_calc_core_pos(u_register_t mpidr); 55*91f16700Schasinglulu * 56*91f16700Schasinglulu * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and 57*91f16700Schasinglulu * AFF0 is thread id. There is only one cluster in ARMv8.2 58*91f16700Schasinglulu * and one thread in current implementation. 59*91f16700Schasinglulu * 60*91f16700Schasinglulu * With this function: CorePos = CoreID (AFF1) 61*91f16700Schasinglulu * we do it with x0 = (x0 >> 8) & 0xff 62*91f16700Schasinglulu * ----------------------------------------------------- 63*91f16700Schasinglulu */ 64*91f16700Schasinglulufunc plat_mediatek_calc_core_pos 65*91f16700Schasinglulu b plat_core_pos_by_mpidr 66*91f16700Schasingluluendfunc plat_mediatek_calc_core_pos 67*91f16700Schasinglulu 68*91f16700Schasinglulu /* ------------------------------------------------------ 69*91f16700Schasinglulu * int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 70*91f16700Schasinglulu * 71*91f16700Schasinglulu * This function implements a part of the critical 72*91f16700Schasinglulu * interface between the psci generic layer and the 73*91f16700Schasinglulu * platform that allows the former to query the platform 74*91f16700Schasinglulu * to convert an MPIDR to a unique linear index. 75*91f16700Schasinglulu * 76*91f16700Schasinglulu * Clobbers: x0-x1 77*91f16700Schasinglulu * ------------------------------------------------------ 78*91f16700Schasinglulu */ 79*91f16700Schasinglulufunc plat_core_pos_by_mpidr 80*91f16700Schasinglulu mov x1, #MPIDR_AFFLVL_MASK 81*91f16700Schasinglulu and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 82*91f16700Schasinglulu ret 83*91f16700Schasingluluendfunc plat_core_pos_by_mpidr 84*91f16700Schasinglulu 85*91f16700Schasinglulu /* -------------------------------------------------------- 86*91f16700Schasinglulu * void platform_mem_init (void); 87*91f16700Schasinglulu * 88*91f16700Schasinglulu * Any memory init, relocation to be done before the 89*91f16700Schasinglulu * platform boots. Called very early in the boot process. 90*91f16700Schasinglulu * -------------------------------------------------------- 91*91f16700Schasinglulu */ 92*91f16700Schasinglulufunc platform_mem_init 93*91f16700Schasinglulu ret 94*91f16700Schasingluluendfunc platform_mem_init 95*91f16700Schasinglulu 96*91f16700Schasinglulufunc plat_reset_handler 97*91f16700Schasinglulu#if CONFIG_MTK_MCUSYS 98*91f16700Schasinglulu mov x10, x30 99*91f16700Schasinglulu bl plat_my_core_pos 100*91f16700Schasinglulu mov x30, x10 101*91f16700Schasinglulu mov w1, #0x1 102*91f16700Schasinglulu lsl w1, w1, w0 103*91f16700Schasinglulu ldr x0, =CPC_MCUSYS_CPU_ON_SW_HINT_SET 104*91f16700Schasinglulu str w1, [x0] 105*91f16700Schasinglulu dsb sy 106*91f16700Schasinglulu#endif 107*91f16700Schasinglulu 108*91f16700Schasinglulu#if CONFIG_MTK_ECC 109*91f16700Schasinglulu mov x10, x30 110*91f16700Schasinglulu /* enable sequence of ecc for cpus */ 111*91f16700Schasinglulu bl disable_core_ecc 112*91f16700Schasinglulu bl ft_ecc_clear_per_core 113*91f16700Schasinglulu bl enable_core_ecc 114*91f16700Schasinglulu mov x30, x10 115*91f16700Schasinglulu#endif 116*91f16700Schasinglulu 117*91f16700Schasinglulu ret 118*91f16700Schasingluluendfunc plat_reset_handler 119