xref: /arm-trusted-firmware/plat/mediatek/drivers/uart/uart8250.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu #ifndef UART8250_H
7*91f16700Schasinglulu #define UART8250_H
8*91f16700Schasinglulu 
9*91f16700Schasinglulu /* UART register */
10*91f16700Schasinglulu #define UART_RBR		0x00	/* Receive buffer register */
11*91f16700Schasinglulu #define UART_DLL		0x00	/* Divisor latch lsb */
12*91f16700Schasinglulu #define UART_THR		0x00	/* Transmit holding register */
13*91f16700Schasinglulu #define UART_DLH		0x04	/* Divisor latch msb */
14*91f16700Schasinglulu #define UART_IER		0x04	/* Interrupt enable register */
15*91f16700Schasinglulu #define UART_FCR		0x08	/* FIFO control register */
16*91f16700Schasinglulu #define UART_LCR		0x0c	/* Line control register */
17*91f16700Schasinglulu #define UART_MCR		0x10	/* Modem control register */
18*91f16700Schasinglulu #define UART_LSR		0x14	/* Line status register */
19*91f16700Schasinglulu #define UART_HIGHSPEED		0x24	/* High speed UART */
20*91f16700Schasinglulu 
21*91f16700Schasinglulu /* FCR */
22*91f16700Schasinglulu #define UART_FCR_FIFO_EN	0x01	/* enable FIFO */
23*91f16700Schasinglulu #define UART_FCR_CLEAR_RCVR	0x02	/* clear the RCVR FIFO */
24*91f16700Schasinglulu #define UART_FCR_CLEAR_XMIT	0x04	/* clear the XMIT FIFO */
25*91f16700Schasinglulu 
26*91f16700Schasinglulu /* LCR */
27*91f16700Schasinglulu #define UART_LCR_WLS_8		0x03	/* 8 bit character length */
28*91f16700Schasinglulu #define UART_LCR_DLAB		0x80	/* divisor latch access bit */
29*91f16700Schasinglulu 
30*91f16700Schasinglulu /* MCR */
31*91f16700Schasinglulu #define UART_MCR_DTR		0x01
32*91f16700Schasinglulu #define UART_MCR_RTS		0x02
33*91f16700Schasinglulu 
34*91f16700Schasinglulu /* LSR */
35*91f16700Schasinglulu #define UART_LSR_DR		0x01	/* Data ready */
36*91f16700Schasinglulu #define UART_LSR_THRE		0x20	/* Xmit holding register empty */
37*91f16700Schasinglulu 
38*91f16700Schasinglulu #endif /* UART8250_H */
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