1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef UART_H 8*91f16700Schasinglulu #define UART_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* UART HW information */ 13*91f16700Schasinglulu #define HW_SUPPORT_UART_PORTS 2 14*91f16700Schasinglulu #define DRV_SUPPORT_UART_PORTS 2 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* console UART clock cg */ 17*91f16700Schasinglulu #define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80) 18*91f16700Schasinglulu #define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84) 19*91f16700Schasinglulu #define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90) 20*91f16700Schasinglulu #define UART0_CLOCK_GATE_BIT (1U<<22) 21*91f16700Schasinglulu #define UART1_CLOCK_GATE_BIT (1U<<23) 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* UART registers */ 24*91f16700Schasinglulu #define UART_RBR(_baseaddr) (_baseaddr + 0x0) 25*91f16700Schasinglulu #define UART_THR(_baseaddr) (_baseaddr + 0x0) 26*91f16700Schasinglulu #define UART_IER(_baseaddr) (_baseaddr + 0x4) 27*91f16700Schasinglulu #define UART_IIR(_baseaddr) (_baseaddr + 0x8) 28*91f16700Schasinglulu #define UART_FCR(_baseaddr) (_baseaddr + 0x8) 29*91f16700Schasinglulu #define UART_LCR(_baseaddr) (_baseaddr + 0xc) 30*91f16700Schasinglulu #define UART_MCR(_baseaddr) (_baseaddr + 0x10) 31*91f16700Schasinglulu #define UART_LSR(_baseaddr) (_baseaddr + 0x14) 32*91f16700Schasinglulu #define UART_MSR(_baseaddr) (_baseaddr + 0x18) 33*91f16700Schasinglulu #define UART_SCR(_baseaddr) (_baseaddr + 0x1c) 34*91f16700Schasinglulu #define UART_DLL(_baseaddr) (_baseaddr + 0x0) 35*91f16700Schasinglulu #define UART_DLH(_baseaddr) (_baseaddr + 0x4) 36*91f16700Schasinglulu #define UART_EFR(_baseaddr) (_baseaddr + 0x8) 37*91f16700Schasinglulu #define UART_XON1(_baseaddr) (_baseaddr + 0x10) 38*91f16700Schasinglulu #define UART_XON2(_baseaddr) (_baseaddr + 0x14) 39*91f16700Schasinglulu #define UART_XOFF1(_baseaddr) (_baseaddr + 0x18) 40*91f16700Schasinglulu #define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c) 41*91f16700Schasinglulu #define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20) 42*91f16700Schasinglulu #define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24) 43*91f16700Schasinglulu #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28) 44*91f16700Schasinglulu #define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c) 45*91f16700Schasinglulu #define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30) 46*91f16700Schasinglulu #define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34) 47*91f16700Schasinglulu #define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38) 48*91f16700Schasinglulu #define UART_GUARD(_baseaddr) (_baseaddr + 0x3c) 49*91f16700Schasinglulu #define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40) 50*91f16700Schasinglulu #define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44) 51*91f16700Schasinglulu #define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48) 52*91f16700Schasinglulu #define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c) 53*91f16700Schasinglulu #define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50) 54*91f16700Schasinglulu #define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54) 55*91f16700Schasinglulu #define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58) 56*91f16700Schasinglulu #define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C) 57*91f16700Schasinglulu #define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0) 58*91f16700Schasinglulu #define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4) 59*91f16700Schasinglulu #define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8) 60*91f16700Schasinglulu #define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC) 61*91f16700Schasinglulu #define UART_LCR_DLAB 0x0080 62*91f16700Schasinglulu #define UART_LCR_MODE_B 0x00bf 63*91f16700Schasinglulu 64*91f16700Schasinglulu enum uart_port_ID { 65*91f16700Schasinglulu UART_PORT0 = 0, 66*91f16700Schasinglulu UART_PORT1 67*91f16700Schasinglulu }; 68*91f16700Schasinglulu 69*91f16700Schasinglulu struct mt_uart_register { 70*91f16700Schasinglulu uint32_t dll; 71*91f16700Schasinglulu uint32_t dlh; 72*91f16700Schasinglulu uint32_t ier; 73*91f16700Schasinglulu uint32_t lcr; 74*91f16700Schasinglulu uint32_t mcr; 75*91f16700Schasinglulu uint32_t fcr; 76*91f16700Schasinglulu uint32_t lsr; 77*91f16700Schasinglulu uint32_t scr; 78*91f16700Schasinglulu uint32_t efr; 79*91f16700Schasinglulu uint32_t highspeed; 80*91f16700Schasinglulu uint32_t sample_count; 81*91f16700Schasinglulu uint32_t sample_point; 82*91f16700Schasinglulu uint32_t fracdiv_l; 83*91f16700Schasinglulu uint32_t fracdiv_m; 84*91f16700Schasinglulu uint32_t escape_en; 85*91f16700Schasinglulu uint32_t guard; 86*91f16700Schasinglulu uint32_t rx_sel; 87*91f16700Schasinglulu }; 88*91f16700Schasinglulu 89*91f16700Schasinglulu struct mt_uart { 90*91f16700Schasinglulu unsigned long base; 91*91f16700Schasinglulu struct mt_uart_register registers; 92*91f16700Schasinglulu }; 93*91f16700Schasinglulu 94*91f16700Schasinglulu /* external API */ 95*91f16700Schasinglulu void mt_uart_save(void); 96*91f16700Schasinglulu void mt_uart_restore(void); 97*91f16700Schasinglulu void mt_console_uart_cg(int on); 98*91f16700Schasinglulu uint32_t mt_console_uart_cg_status(void); 99*91f16700Schasinglulu 100*91f16700Schasinglulu #endif /* __UART_H__ */ 101