1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_TIMER_H 8*91f16700Schasinglulu #define MT_TIMER_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define SYSTIMER_BASE (0x10017000) 11*91f16700Schasinglulu #define CNTCR_REG (SYSTIMER_BASE + 0x0) 12*91f16700Schasinglulu #define CNTSR_REG (SYSTIMER_BASE + 0x4) 13*91f16700Schasinglulu #define CNTSYS_L_REG (SYSTIMER_BASE + 0x8) 14*91f16700Schasinglulu #define CNTSYS_H_REG (SYSTIMER_BASE + 0xc) 15*91f16700Schasinglulu #define CNTWACR_REG (SYSTIMER_BASE + 0x10) 16*91f16700Schasinglulu #define CNTRACR_REG (SYSTIMER_BASE + 0x14) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define TIEO_EN (1 << 3) 19*91f16700Schasinglulu #define COMP_15_EN (1 << 10) 20*91f16700Schasinglulu #define COMP_20_EN (1 << 11) 21*91f16700Schasinglulu #define COMP_25_EN (1 << 12) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN) 24*91f16700Schasinglulu #define COMP_15_MASK (COMP_15_EN) 25*91f16700Schasinglulu #define COMP_20_MASK (COMP_20_EN | TIEO_EN) 26*91f16700Schasinglulu #define COMP_25_MASK (COMP_20_EN | COMP_25_EN) 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U) 29*91f16700Schasinglulu #define CNT_READ_ACCESS_CTL_MASK (0x3FFFFFFU) 30*91f16700Schasinglulu 31*91f16700Schasinglulu void sched_clock_init(uint64_t normal_base, uint64_t atf_base); 32*91f16700Schasinglulu uint64_t sched_clock(void); 33*91f16700Schasinglulu int mt_systimer_init(void); 34*91f16700Schasinglulu 35*91f16700Schasinglulu #endif /* MT_TIMER_H */ 36