1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu #include <lib/mtk_init/mtk_init.h> 11*91f16700Schasinglulu #include <mt_timer.h> 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu uint64_t normal_time_base; 15*91f16700Schasinglulu uint64_t atf_time_base; 16*91f16700Schasinglulu 17*91f16700Schasinglulu void sched_clock_init(uint64_t normal_base, uint64_t atf_base) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu normal_time_base += normal_base; 20*91f16700Schasinglulu atf_time_base = atf_base; 21*91f16700Schasinglulu } 22*91f16700Schasinglulu 23*91f16700Schasinglulu uint64_t sched_clock(void) 24*91f16700Schasinglulu { 25*91f16700Schasinglulu uint64_t cval; 26*91f16700Schasinglulu uint64_t rel_base; 27*91f16700Schasinglulu 28*91f16700Schasinglulu rel_base = read_cntpct_el0() - atf_time_base; 29*91f16700Schasinglulu cval = ((rel_base * 1000U) / SYS_COUNTER_FREQ_IN_MHZ) 30*91f16700Schasinglulu - normal_time_base; 31*91f16700Schasinglulu return cval; 32*91f16700Schasinglulu } 33*91f16700Schasinglulu 34*91f16700Schasinglulu int mt_systimer_init(void) 35*91f16700Schasinglulu { 36*91f16700Schasinglulu INFO("[%s] systimer initialization\n", __func__); 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* Enable access in NS mode */ 39*91f16700Schasinglulu mmio_write_32(CNTWACR_REG, CNT_WRITE_ACCESS_CTL_MASK); 40*91f16700Schasinglulu mmio_write_32(CNTRACR_REG, CNT_READ_ACCESS_CTL_MASK); 41*91f16700Schasinglulu 42*91f16700Schasinglulu return 0; 43*91f16700Schasinglulu } 44*91f16700Schasinglulu MTK_PLAT_SETUP_0_INIT(mt_systimer_init); 45