1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu /**************************************************************** 8*91f16700Schasinglulu * Auto generated by DE, please DO NOT modify this file directly. 9*91f16700Schasinglulu *****************************************************************/ 10*91f16700Schasinglulu 11*91f16700Schasinglulu #ifndef MT_SPM_PMIC_WRAP_H 12*91f16700Schasinglulu #define MT_SPM_PMIC_WRAP_H 13*91f16700Schasinglulu 14*91f16700Schasinglulu enum pmic_wrap_phase_id { 15*91f16700Schasinglulu PMIC_WRAP_PHASE_ALLINONE = 0, 16*91f16700Schasinglulu NR_PMIC_WRAP_PHASE, 17*91f16700Schasinglulu }; 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* IDX mapping */ 20*91f16700Schasinglulu enum { 21*91f16700Schasinglulu CMD_0 = 0, /* PMIC_WRAP_PHASE_ALLINONE */ 22*91f16700Schasinglulu CMD_1, 23*91f16700Schasinglulu CMD_2, 24*91f16700Schasinglulu CMD_3, 25*91f16700Schasinglulu CMD_4, 26*91f16700Schasinglulu CMD_5, 27*91f16700Schasinglulu CMD_6, 28*91f16700Schasinglulu CMD_7, 29*91f16700Schasinglulu CMD_8, 30*91f16700Schasinglulu CMD_9, 31*91f16700Schasinglulu CMD_10, 32*91f16700Schasinglulu CMD_11, 33*91f16700Schasinglulu CMD_12, 34*91f16700Schasinglulu CMD_13, 35*91f16700Schasinglulu CMD_14, 36*91f16700Schasinglulu CMD_15, 37*91f16700Schasinglulu NR_IDX_ALL, 38*91f16700Schasinglulu }; 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* APIs */ 41*91f16700Schasinglulu void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); 42*91f16700Schasinglulu void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx, 43*91f16700Schasinglulu unsigned int cmd_wdata); 44*91f16700Schasinglulu uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx); 45*91f16700Schasinglulu void mt_spm_dump_pmic_warp_reg(void); 46*91f16700Schasinglulu 47*91f16700Schasinglulu #endif /* MT_SPM_PMIC_WRAP_H */ 48