1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_SPM_COND_H 8*91f16700Schasinglulu #define MT_SPM_COND_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lpm/mt_lp_rm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu enum plat_spm_cond { 13*91f16700Schasinglulu PLAT_SPM_COND_MTCMOS1 = 0, 14*91f16700Schasinglulu PLAT_SPM_COND_MTCMOS2, 15*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_0, 16*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_1, 17*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_2, 18*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_3, 19*91f16700Schasinglulu PLAT_SPM_COND_CG_INFRA_4, 20*91f16700Schasinglulu PLAT_SPM_COND_CG_PERI_0, 21*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS0_0, 22*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS0_1, 23*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS1_0, 24*91f16700Schasinglulu PLAT_SPM_COND_CG_VPPSYS1_1, 25*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS0_0, 26*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS0_1, 27*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS1_0, 28*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS1_1, 29*91f16700Schasinglulu PLAT_SPM_COND_CG_VDOSYS1_2, 30*91f16700Schasinglulu PLAT_SPM_COND_MAX, 31*91f16700Schasinglulu }; 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* For PLL id >= PLAT_SPM_COND_PLL_MAX is not checked in idle condition */ 34*91f16700Schasinglulu enum plat_spm_cond_pll { 35*91f16700Schasinglulu PLAT_SPM_COND_PLL_UNIVPLL = 0, 36*91f16700Schasinglulu PLAT_SPM_COND_PLL_MFGPLL, 37*91f16700Schasinglulu PLAT_SPM_COND_PLL_MSDCPLL, 38*91f16700Schasinglulu PLAT_SPM_COND_PLL_TVDPLL1, 39*91f16700Schasinglulu PLAT_SPM_COND_PLL_TVDPLL2, 40*91f16700Schasinglulu PLAT_SPM_COND_PLL_MMPLL, 41*91f16700Schasinglulu PLAT_SPM_COND_PLL_ETHPLL, 42*91f16700Schasinglulu PLAT_SPM_COND_PLL_IMGPLL, 43*91f16700Schasinglulu PLAT_SPM_COND_PLL_APLL1, 44*91f16700Schasinglulu PLAT_SPM_COND_PLL_APLL2, 45*91f16700Schasinglulu PLAT_SPM_COND_PLL_APLL3, 46*91f16700Schasinglulu PLAT_SPM_COND_PLL_APLL4, 47*91f16700Schasinglulu PLAT_SPM_COND_PLL_APLL5, 48*91f16700Schasinglulu PLAT_SPM_COND_PLL_MAX, 49*91f16700Schasinglulu }; 50*91f16700Schasinglulu 51*91f16700Schasinglulu #define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL) 52*91f16700Schasinglulu #define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL) 53*91f16700Schasinglulu #define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL) 54*91f16700Schasinglulu #define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL) 55*91f16700Schasinglulu #define PLL_BIT_TVDPLL1 BIT(PLAT_SPM_COND_PLL_TVDPLL1) 56*91f16700Schasinglulu #define PLL_BIT_TVDPLL2 BIT(PLAT_SPM_COND_PLL_TVDPLL2) 57*91f16700Schasinglulu #define PLL_BIT_ETHPLL BIT(PLAT_SPM_COND_PLL_ETHPLL) 58*91f16700Schasinglulu #define PLL_BIT_IMGPLL BIT(PLAT_SPM_COND_PLL_IMGPLL) 59*91f16700Schasinglulu #define PLL_BIT_APLL1 BIT(PLAT_SPM_COND_PLL_APLL1) 60*91f16700Schasinglulu #define PLL_BIT_APLL2 BIT(PLAT_SPM_COND_PLL_APLL2) 61*91f16700Schasinglulu #define PLL_BIT_APLL3 BIT(PLAT_SPM_COND_PLL_APLL3) 62*91f16700Schasinglulu #define PLL_BIT_APLL4 BIT(PLAT_SPM_COND_PLL_APLL4) 63*91f16700Schasinglulu #define PLL_BIT_APLL5 BIT(PLAT_SPM_COND_PLL_APLL5) 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* 66*91f16700Schasinglulu * Definition about SPM_COND_CHECK_BLOCKED 67*91f16700Schasinglulu * bit[00:16]: cg blocking index 68*91f16700Schasinglulu * bit[17:29]: pll blocking index 69*91f16700Schasinglulu * bit[30]: pll blocking information 70*91f16700Schasinglulu * bit[31]: idle condition check fail 71*91f16700Schasinglulu */ 72*91f16700Schasinglulu #define SPM_COND_BLOCKED_CG_IDX (0) 73*91f16700Schasinglulu #define SPM_COND_BLOCKED_PLL_IDX (17) 74*91f16700Schasinglulu #define SPM_COND_CHECK_BLOCKED_PLL BIT(30) 75*91f16700Schasinglulu #define SPM_COND_CHECK_FAIL BIT(31) 76*91f16700Schasinglulu 77*91f16700Schasinglulu struct mt_spm_cond_tables { 78*91f16700Schasinglulu char *name; 79*91f16700Schasinglulu unsigned int table_cg[PLAT_SPM_COND_MAX]; 80*91f16700Schasinglulu unsigned int table_pll; 81*91f16700Schasinglulu unsigned int table_all_pll; 82*91f16700Schasinglulu void *priv; 83*91f16700Schasinglulu }; 84*91f16700Schasinglulu 85*91f16700Schasinglulu unsigned int mt_spm_cond_check(int state_id, 86*91f16700Schasinglulu const struct mt_spm_cond_tables *src, 87*91f16700Schasinglulu const struct mt_spm_cond_tables *dest, 88*91f16700Schasinglulu struct mt_spm_cond_tables *res); 89*91f16700Schasinglulu unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src, 90*91f16700Schasinglulu const struct mt_spm_cond_tables *dest, 91*91f16700Schasinglulu struct mt_spm_cond_tables *res); 92*91f16700Schasinglulu int mt_spm_cond_update(struct mt_resource_constraint **con, unsigned int num, 93*91f16700Schasinglulu int stateid, void *priv); 94*91f16700Schasinglulu 95*91f16700Schasinglulu #endif 96