1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PMIC_WRAP_INIT_COMMON_H 8*91f16700Schasinglulu #define PMIC_WRAP_INIT_COMMON_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include "platform_def.h" 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* external API */ 15*91f16700Schasinglulu int32_t pwrap_read(uint32_t adr, uint32_t *rdata); 16*91f16700Schasinglulu int32_t pwrap_write(uint32_t adr, uint32_t wdata); 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define GET_WACS_FSM(x) ((x >> 1) & 0x7) 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* macro for SWINF_FSM */ 21*91f16700Schasinglulu #define SWINF_FSM_IDLE (0x00) 22*91f16700Schasinglulu #define SWINF_FSM_REQ (0x02) 23*91f16700Schasinglulu #define SWINF_FSM_WFDLE (0x04) 24*91f16700Schasinglulu #define SWINF_FSM_WFVLDCLR (0x06) 25*91f16700Schasinglulu #define SWINF_INIT_DONE (0x01) 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* timeout setting */ 28*91f16700Schasinglulu #define PWRAP_READ_US (1000) 29*91f16700Schasinglulu #define PWRAP_WAIT_IDLE_US (1000) 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* error information flag */ 32*91f16700Schasinglulu enum pwrap_errno { 33*91f16700Schasinglulu E_PWR_INVALID_ARG = 1, 34*91f16700Schasinglulu E_PWR_INVALID_RW = 2, 35*91f16700Schasinglulu E_PWR_INVALID_ADDR = 3, 36*91f16700Schasinglulu E_PWR_INVALID_WDAT = 4, 37*91f16700Schasinglulu E_PWR_INVALID_OP_MANUAL = 5, 38*91f16700Schasinglulu E_PWR_NOT_IDLE_STATE = 6, 39*91f16700Schasinglulu E_PWR_NOT_INIT_DONE = 7, 40*91f16700Schasinglulu E_PWR_NOT_INIT_DONE_READ = 8, 41*91f16700Schasinglulu E_PWR_WAIT_IDLE_TIMEOUT = 9, 42*91f16700Schasinglulu E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, 43*91f16700Schasinglulu E_PWR_INIT_SIDLY_FAIL = 11, 44*91f16700Schasinglulu E_PWR_RESET_TIMEOUT = 12, 45*91f16700Schasinglulu E_PWR_TIMEOUT = 13, 46*91f16700Schasinglulu E_PWR_INIT_RESET_SPI = 20, 47*91f16700Schasinglulu E_PWR_INIT_SIDLY = 21, 48*91f16700Schasinglulu E_PWR_INIT_REG_CLOCK = 22, 49*91f16700Schasinglulu E_PWR_INIT_ENABLE_PMIC = 23, 50*91f16700Schasinglulu E_PWR_INIT_DIO = 24, 51*91f16700Schasinglulu E_PWR_INIT_CIPHER = 25, 52*91f16700Schasinglulu E_PWR_INIT_WRITE_TEST = 26, 53*91f16700Schasinglulu E_PWR_INIT_ENABLE_CRC = 27, 54*91f16700Schasinglulu E_PWR_INIT_ENABLE_DEWRAP = 28, 55*91f16700Schasinglulu E_PWR_INIT_ENABLE_EVENT = 29, 56*91f16700Schasinglulu E_PWR_READ_TEST_FAIL = 30, 57*91f16700Schasinglulu E_PWR_WRITE_TEST_FAIL = 31, 58*91f16700Schasinglulu E_PWR_SWITCH_DIO = 32, 59*91f16700Schasinglulu }; 60*91f16700Schasinglulu 61*91f16700Schasinglulu #endif /* PMIC_WRAP_INIT_COMMON_H */ 62