1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <inttypes.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <common/debug.h> 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <mt_dp.h> 12*91f16700Schasinglulu #include <mtk_sip_svc.h> 13*91f16700Schasinglulu #include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset, 16*91f16700Schasinglulu uint32_t value, uint32_t mask) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu uint32_t reg = (is_edp != 0U) ? EDP_SEC_BASE : DP_SEC_BASE; 19*91f16700Schasinglulu 20*91f16700Schasinglulu mmio_clrsetbits_32(reg + offset, mask, value); 21*91f16700Schasinglulu 22*91f16700Schasinglulu return mmio_read_32(reg + offset); 23*91f16700Schasinglulu } 24*91f16700Schasinglulu 25*91f16700Schasinglulu int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val) 26*91f16700Schasinglulu { 27*91f16700Schasinglulu int32_t ret = 0L; 28*91f16700Schasinglulu uint32_t is_edp = 0UL; 29*91f16700Schasinglulu uint32_t regval = 0UL; 30*91f16700Schasinglulu uint32_t regmsk = 0UL; 31*91f16700Schasinglulu uint32_t fldmask = 0UL; 32*91f16700Schasinglulu 33*91f16700Schasinglulu if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) { 34*91f16700Schasinglulu INFO("dp_secure_handler error cmd 0x%" PRIx64 "\n", cmd); 35*91f16700Schasinglulu return MTK_SIP_E_INVALID_PARAM; 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu switch (cmd) { 39*91f16700Schasinglulu case DP_ATF_DP_VIDEO_UNMUTE: 40*91f16700Schasinglulu INFO("[%s] DP_ATF_DP_VIDEO_UNMUTE\n", __func__); 41*91f16700Schasinglulu is_edp = DP_ATF_TYPE_DP; 42*91f16700Schasinglulu ret = MTK_SIP_E_SUCCESS; 43*91f16700Schasinglulu break; 44*91f16700Schasinglulu case DP_ATF_EDP_VIDEO_UNMUTE: 45*91f16700Schasinglulu INFO("[%s] DP_ATF_EDP_VIDEO_UNMUTE\n", __func__); 46*91f16700Schasinglulu is_edp = DP_ATF_TYPE_EDP; 47*91f16700Schasinglulu ret = MTK_SIP_E_SUCCESS; 48*91f16700Schasinglulu break; 49*91f16700Schasinglulu default: 50*91f16700Schasinglulu ret = MTK_SIP_E_INVALID_PARAM; 51*91f16700Schasinglulu break; 52*91f16700Schasinglulu } 53*91f16700Schasinglulu 54*91f16700Schasinglulu if (ret == MTK_SIP_E_SUCCESS) { 55*91f16700Schasinglulu regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK | 56*91f16700Schasinglulu VIDEO_MUTE_SW_SECURE_FLDMASK); 57*91f16700Schasinglulu if (para > 0U) { 58*91f16700Schasinglulu fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK; 59*91f16700Schasinglulu } else { 60*91f16700Schasinglulu fldmask = 0; 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63*91f16700Schasinglulu regval = (VIDEO_MUTE_SEL_SECURE_FLDMASK | fldmask); 64*91f16700Schasinglulu *val = dp_write_sec_reg(is_edp, DP_TX_SECURE_REG11, 65*91f16700Schasinglulu regval, regmsk); 66*91f16700Schasinglulu } 67*91f16700Schasinglulu 68*91f16700Schasinglulu return ret; 69*91f16700Schasinglulu } 70*91f16700Schasinglulu 71*91f16700Schasinglulu u_register_t mtk_dp_sip_handler(u_register_t x1, u_register_t x2, 72*91f16700Schasinglulu u_register_t x3, u_register_t x4, 73*91f16700Schasinglulu void *handle, struct smccc_res *smccc_ret) 74*91f16700Schasinglulu { 75*91f16700Schasinglulu uint32_t ret_val; 76*91f16700Schasinglulu 77*91f16700Schasinglulu return dp_secure_handler(x1, x2, &ret_val); 78*91f16700Schasinglulu } 79*91f16700Schasinglulu DECLARE_SMC_HANDLER(MTK_SIP_DP_CONTROL, mtk_dp_sip_handler); 80