1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_DFD_H 8*91f16700Schasinglulu #define PLAT_DFD_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0) 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) 16*91f16700Schasinglulu #define PLAT_MTK_DFD_READ_MAGIC (0x99716151) 17*91f16700Schasinglulu #define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define MTK_DRM_LATCH_CTL1 (DRM_BASE + 0x40) 20*91f16700Schasinglulu #define MTK_DRM_LATCH_CTL2 (DRM_BASE + 0x44) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define MTK_WDT_BASE (RGU_BASE) 23*91f16700Schasinglulu #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10) 24*91f16700Schasinglulu #define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define MCU_BIU_BASE (MCUCFG_BASE) 27*91f16700Schasinglulu #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) 28*91f16700Schasinglulu #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) 29*91f16700Schasinglulu #define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08) 30*91f16700Schasinglulu #define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C) 31*91f16700Schasinglulu #define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10) 32*91f16700Schasinglulu #define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C) 33*91f16700Schasinglulu #define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20) 34*91f16700Schasinglulu #define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24) 35*91f16700Schasinglulu #define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28) 36*91f16700Schasinglulu #define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30) 37*91f16700Schasinglulu #define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34) 38*91f16700Schasinglulu #define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c) 39*91f16700Schasinglulu #define DFD_V30_CTL (MISC1_CFG_BASE + 0x48) 40*91f16700Schasinglulu #define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C) 41*91f16700Schasinglulu #define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50) 42*91f16700Schasinglulu #define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58) 43*91f16700Schasinglulu #define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C) 44*91f16700Schasinglulu #define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60) 45*91f16700Schasinglulu #define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8) 46*91f16700Schasinglulu #define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC) 47*91f16700Schasinglulu #define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8) 48*91f16700Schasinglulu #define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC) 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8) 51*91f16700Schasinglulu #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC) 52*91f16700Schasinglulu #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0) 53*91f16700Schasinglulu #define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4) 54*91f16700Schasinglulu #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0) 55*91f16700Schasinglulu #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4) 56*91f16700Schasinglulu #define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC) 57*91f16700Schasinglulu 58*91f16700Schasinglulu #define DFD_O_PROTECT_EN_REG (0x10001220) 59*91f16700Schasinglulu #define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C) 60*91f16700Schasinglulu #define DFD_O_SET_BASEADDR_REG (0x10043000) 61*91f16700Schasinglulu #define DFD_O_REG_0 (0x10001390) 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define DFD_CACHE_DUMP_ENABLE (1U) 64*91f16700Schasinglulu #define DFD_PARITY_ERR_TRIGGER (2U) 65*91f16700Schasinglulu 66*91f16700Schasinglulu #define DFD_V35_TAP_EN_VAL (0x43FF) 67*91f16700Schasinglulu #define DFD_V35_SEQ0_0_VAL (0x63668820) 68*91f16700Schasinglulu #define DFD_READ_ADDR_VAL (0x40000008) 69*91f16700Schasinglulu #define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF) 70*91f16700Schasinglulu 71*91f16700Schasinglulu #define MTK_WDT_LATCH_CTL2_VAL (0x9507FFFF) 72*91f16700Schasinglulu #define MTK_WDT_INTERVAL_VAL (0x6600000A) 73*91f16700Schasinglulu #define MTK_DRM_LATCH_CTL2_VAL (0x950607D0) 74*91f16700Schasinglulu #define MTK_DRM_LATCH_CTL2_CACHE_VAL (0x95065DC0) 75*91f16700Schasinglulu 76*91f16700Schasinglulu #define MTK_DRM_LATCH_CTL1_VAL (0x95000013) 77*91f16700Schasinglulu 78*91f16700Schasinglulu #endif /* PLAT_DFD_H */ 79