1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #include <arch_helpers.h> 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu #include <dfd.h> 10*91f16700Schasinglulu #include <plat_dfd.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu static uint64_t dfd_cache_dump; 13*91f16700Schasinglulu static bool dfd_enabled; 14*91f16700Schasinglulu static uint64_t dfd_base_addr; 15*91f16700Schasinglulu static uint64_t dfd_chain_length; 16*91f16700Schasinglulu 17*91f16700Schasinglulu void dfd_setup(uint64_t base_addr, uint64_t chain_length, uint64_t cache_dump) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL); 20*91f16700Schasinglulu mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL); 21*91f16700Schasinglulu mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL); 22*91f16700Schasinglulu 23*91f16700Schasinglulu mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, BIT(2)); 24*91f16700Schasinglulu mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1); 25*91f16700Schasinglulu sync_writel(DFD_INTERNAL_CTL, 0x5); 26*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); 27*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); 28*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); 29*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); 30*91f16700Schasinglulu 31*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB); 32*91f16700Schasinglulu mmio_write_32(DFD_CHAIN_LENGTH0, chain_length); 33*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0); 34*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1); 35*91f16700Schasinglulu 36*91f16700Schasinglulu mmio_write_32(DFD_TEST_SI_0, 0x0); 37*91f16700Schasinglulu mmio_write_32(DFD_TEST_SI_1, 0x0); 38*91f16700Schasinglulu mmio_write_32(DFD_TEST_SI_2, 0x0); 39*91f16700Schasinglulu mmio_write_32(DFD_TEST_SI_3, 0x0); 40*91f16700Schasinglulu 41*91f16700Schasinglulu sync_writel(DFD_POWER_CTL, 0xF9); 42*91f16700Schasinglulu sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); 43*91f16700Schasinglulu sync_writel(DFD_V30_CTL, 0xD); 44*91f16700Schasinglulu 45*91f16700Schasinglulu mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24); 46*91f16700Schasinglulu mmio_write_32(DFD_O_REG_0, 0); 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* setup global variables for suspend and resume */ 49*91f16700Schasinglulu dfd_enabled = true; 50*91f16700Schasinglulu dfd_base_addr = base_addr; 51*91f16700Schasinglulu dfd_chain_length = chain_length; 52*91f16700Schasinglulu dfd_cache_dump = cache_dump; 53*91f16700Schasinglulu 54*91f16700Schasinglulu if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) { 55*91f16700Schasinglulu mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL); 56*91f16700Schasinglulu sync_writel(DFD_V35_ENABLE, 0x1); 57*91f16700Schasinglulu sync_writel(DFD_V35_TAP_NUMBER, 0xB); 58*91f16700Schasinglulu sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); 59*91f16700Schasinglulu sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* Cache dump only mode */ 62*91f16700Schasinglulu sync_writel(DFD_V35_CTL, 0x1); 63*91f16700Schasinglulu mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF); 64*91f16700Schasinglulu mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL); 65*91f16700Schasinglulu mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL); 66*91f16700Schasinglulu mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL); 67*91f16700Schasinglulu mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL); 68*91f16700Schasinglulu 69*91f16700Schasinglulu if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) { 70*91f16700Schasinglulu sync_writel(DFD_HW_TRIGGER_MASK, 0xC); 71*91f16700Schasinglulu mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); 72*91f16700Schasinglulu } 73*91f16700Schasinglulu } 74*91f16700Schasinglulu dsbsy(); 75*91f16700Schasinglulu } 76*91f16700Schasinglulu 77*91f16700Schasinglulu void dfd_resume(void) 78*91f16700Schasinglulu { 79*91f16700Schasinglulu if (dfd_enabled == true) { 80*91f16700Schasinglulu dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump); 81*91f16700Schasinglulu } 82*91f16700Schasinglulu } 83