1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #include <arch_helpers.h> 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu #include <dfd.h> 10*91f16700Schasinglulu #include <mtk_sip_svc.h> 11*91f16700Schasinglulu #include <plat_dfd.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, 14*91f16700Schasinglulu u_register_t arg2, u_register_t arg3, 15*91f16700Schasinglulu void *handle, struct smccc_res *smccc_ret) 16*91f16700Schasinglulu { 17*91f16700Schasinglulu int ret = MTK_SIP_E_SUCCESS; 18*91f16700Schasinglulu 19*91f16700Schasinglulu switch (arg0) { 20*91f16700Schasinglulu case PLAT_MTK_DFD_SETUP_MAGIC: 21*91f16700Schasinglulu INFO("[%s] DFD setup call from kernel\n", __func__); 22*91f16700Schasinglulu dfd_setup(arg1, arg2, arg3); 23*91f16700Schasinglulu break; 24*91f16700Schasinglulu case PLAT_MTK_DFD_READ_MAGIC: 25*91f16700Schasinglulu /* only allow to access DFD register base + 0x200 */ 26*91f16700Schasinglulu if (arg1 <= 0x200) { 27*91f16700Schasinglulu ret = mmio_read_32(MISC1_CFG_BASE + arg1); 28*91f16700Schasinglulu } 29*91f16700Schasinglulu break; 30*91f16700Schasinglulu case PLAT_MTK_DFD_WRITE_MAGIC: 31*91f16700Schasinglulu /* only allow to access DFD register base + 0x200 */ 32*91f16700Schasinglulu if (arg1 <= 0x200) { 33*91f16700Schasinglulu sync_writel(MISC1_CFG_BASE + arg1, arg2); 34*91f16700Schasinglulu } 35*91f16700Schasinglulu break; 36*91f16700Schasinglulu default: 37*91f16700Schasinglulu ret = MTK_SIP_E_INVALID_PARAM; 38*91f16700Schasinglulu break; 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu return ret; 42*91f16700Schasinglulu } 43*91f16700Schasinglulu DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_DFD, dfd_smc_dispatcher); 44