1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu #include <lib/mtk_init/mtk_init.h> 10*91f16700Schasinglulu #include <mtk_dcm.h> 11*91f16700Schasinglulu #include <mtk_dcm_utils.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu static void dcm_armcore(bool mode) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 16*91f16700Schasinglulu dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 17*91f16700Schasinglulu dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 18*91f16700Schasinglulu } 19*91f16700Schasinglulu 20*91f16700Schasinglulu static void dcm_mcusys(bool on) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu dcm_mp_cpusys_top_adb_dcm(on); 23*91f16700Schasinglulu dcm_mp_cpusys_top_apb_dcm(on); 24*91f16700Schasinglulu dcm_mp_cpusys_top_cpubiu_dcm(on); 25*91f16700Schasinglulu dcm_mp_cpusys_top_misc_dcm(on); 26*91f16700Schasinglulu dcm_mp_cpusys_top_mp0_qdcm(on); 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* CPCCFG_REG */ 29*91f16700Schasinglulu dcm_cpccfg_reg_emi_wfifo(on); 30*91f16700Schasinglulu dcm_mp_cpusys_top_last_cor_idle_dcm(on); 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu static void dcm_stall(bool on) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu dcm_mp_cpusys_top_core_stall_dcm(on); 36*91f16700Schasinglulu dcm_mp_cpusys_top_fcm_stall_dcm(on); 37*91f16700Schasinglulu } 38*91f16700Schasinglulu 39*91f16700Schasinglulu static bool check_dcm_state(void) 40*91f16700Schasinglulu { 41*91f16700Schasinglulu bool ret = true; 42*91f16700Schasinglulu 43*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 44*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 45*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 46*91f16700Schasinglulu 47*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 48*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 49*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 50*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 51*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 52*91f16700Schasinglulu ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 53*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 54*91f16700Schasinglulu 55*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 56*91f16700Schasinglulu ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 57*91f16700Schasinglulu 58*91f16700Schasinglulu return ret; 59*91f16700Schasinglulu } 60*91f16700Schasinglulu 61*91f16700Schasinglulu bool dcm_check_state(uintptr_t addr, unsigned int mask, unsigned int compare) 62*91f16700Schasinglulu { 63*91f16700Schasinglulu return ((mmio_read_32(addr) & mask) == compare); 64*91f16700Schasinglulu } 65*91f16700Schasinglulu 66*91f16700Schasinglulu int dcm_set_init(void) 67*91f16700Schasinglulu { 68*91f16700Schasinglulu int ret; 69*91f16700Schasinglulu 70*91f16700Schasinglulu dcm_armcore(true); 71*91f16700Schasinglulu dcm_mcusys(true); 72*91f16700Schasinglulu dcm_stall(true); 73*91f16700Schasinglulu 74*91f16700Schasinglulu if (check_dcm_state() == false) { 75*91f16700Schasinglulu ERROR("Failed to set default dcm on!!\n"); 76*91f16700Schasinglulu ret = -1; 77*91f16700Schasinglulu } else { 78*91f16700Schasinglulu INFO("%s, dcm pass\n", __func__); 79*91f16700Schasinglulu ret = 0; 80*91f16700Schasinglulu } 81*91f16700Schasinglulu 82*91f16700Schasinglulu return ret; 83*91f16700Schasinglulu } 84*91f16700Schasinglulu MTK_PLAT_SETUP_0_INIT(dcm_set_init); 85