1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef MT_SMP_H 8*91f16700Schasinglulu #define MT_SMP_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define CPU_PWR_STATUS (MCUCFG_BASE + 0xA840) 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define SMP_CORE_TIMEOUT_MAX (50000) 16*91f16700Schasinglulu #define DO_SMP_CORE_ON_WAIT_TIMEOUT(k_cnt) ({ \ 17*91f16700Schasinglulu CPU_PM_ASSERT(k_cnt < SMP_CORE_TIMEOUT_MAX); \ 18*91f16700Schasinglulu k_cnt++; udelay(1); }) 19*91f16700Schasinglulu 20*91f16700Schasinglulu void mt_smp_core_init_arch(unsigned int cluster, unsigned int cpu, int arm64, 21*91f16700Schasinglulu struct cpu_pwr_ctrl *pwr_ctrl); 22*91f16700Schasinglulu void mt_smp_core_bootup_address_set(struct cpu_pwr_ctrl *pwr_ctrl, uintptr_t entry); 23*91f16700Schasinglulu int mt_smp_power_core_on(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl); 24*91f16700Schasinglulu int mt_smp_power_core_off(struct cpu_pwr_ctrl *pwr_ctrl); 25*91f16700Schasinglulu void mt_smp_init(void); 26*91f16700Schasinglulu 27*91f16700Schasinglulu #endif /* MT_SMP_H */ 28