1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLAT_MT_CIRQ_H 8*91f16700Schasinglulu #define PLAT_MT_CIRQ_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu enum { 14*91f16700Schasinglulu IRQ_MASK_HEADER = 0xF1F1F1F1, 15*91f16700Schasinglulu IRQ_MASK_FOOTER = 0xF2F2F2F2 16*91f16700Schasinglulu }; 17*91f16700Schasinglulu 18*91f16700Schasinglulu struct mtk_irq_mask { 19*91f16700Schasinglulu uint32_t header; /* for error checking */ 20*91f16700Schasinglulu uint32_t mask0; 21*91f16700Schasinglulu uint32_t mask1; 22*91f16700Schasinglulu uint32_t mask2; 23*91f16700Schasinglulu uint32_t mask3; 24*91f16700Schasinglulu uint32_t mask4; 25*91f16700Schasinglulu uint32_t mask5; 26*91f16700Schasinglulu uint32_t mask6; 27*91f16700Schasinglulu uint32_t mask7; 28*91f16700Schasinglulu uint32_t mask8; 29*91f16700Schasinglulu uint32_t mask9; 30*91f16700Schasinglulu uint32_t mask10; 31*91f16700Schasinglulu uint32_t mask11; 32*91f16700Schasinglulu uint32_t mask12; 33*91f16700Schasinglulu uint32_t footer; /* for error checking */ 34*91f16700Schasinglulu }; 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* 37*91f16700Schasinglulu * Define hardware register 38*91f16700Schasinglulu */ 39*91f16700Schasinglulu #define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000)) 40*91f16700Schasinglulu #define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080)) 41*91f16700Schasinglulu #define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100)) 42*91f16700Schasinglulu #define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180)) 43*91f16700Schasinglulu #define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200)) 44*91f16700Schasinglulu #define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280)) 45*91f16700Schasinglulu #define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300)) 46*91f16700Schasinglulu #define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380)) 47*91f16700Schasinglulu #define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400)) 48*91f16700Schasinglulu #define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480)) 49*91f16700Schasinglulu #define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500)) 50*91f16700Schasinglulu #define CIRQ_CON (SYS_CIRQ_BASE + U(0x600)) 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* 53*91f16700Schasinglulu * Register placement 54*91f16700Schasinglulu */ 55*91f16700Schasinglulu #define CIRQ_CON_EN_BITS U(0) 56*91f16700Schasinglulu #define CIRQ_CON_EDGE_ONLY_BITS U(1) 57*91f16700Schasinglulu #define CIRQ_CON_FLUSH_BITS U(2) 58*91f16700Schasinglulu #define CIRQ_CON_SW_RST_BITS U(20) 59*91f16700Schasinglulu #define CIRQ_CON_EVENT_BITS U(31) 60*91f16700Schasinglulu #define CIRQ_CON_BITS_MASK U(0x7) 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* 63*91f16700Schasinglulu * Register setting 64*91f16700Schasinglulu */ 65*91f16700Schasinglulu #define CIRQ_CON_EN U(0x1) 66*91f16700Schasinglulu #define CIRQ_CON_EDGE_ONLY U(0x1) 67*91f16700Schasinglulu #define CIRQ_CON_FLUSH U(0x1) 68*91f16700Schasinglulu #define CIRQ_SW_RESET U(0x1) 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* 71*91f16700Schasinglulu * Define constant 72*91f16700Schasinglulu */ 73*91f16700Schasinglulu #define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U) 74*91f16700Schasinglulu 75*91f16700Schasinglulu #define MT_CIRQ_POL_NEG U(0) 76*91f16700Schasinglulu #define MT_CIRQ_POL_POS U(1) 77*91f16700Schasinglulu 78*91f16700Schasinglulu #define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START)) 79*91f16700Schasinglulu #define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START)) 80*91f16700Schasinglulu 81*91f16700Schasinglulu /* GIC sensitive */ 82*91f16700Schasinglulu #define SENS_EDGE U(0x2) 83*91f16700Schasinglulu #define SENS_LEVEL U(0x1) 84*91f16700Schasinglulu 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* 87*91f16700Schasinglulu * Define function prototypes. 88*91f16700Schasinglulu */ 89*91f16700Schasinglulu int mt_cirq_test(void); 90*91f16700Schasinglulu void mt_cirq_dump_reg(void); 91*91f16700Schasinglulu int mt_irq_mask_restore(struct mtk_irq_mask *mask); 92*91f16700Schasinglulu int mt_irq_mask_all(struct mtk_irq_mask *mask); 93*91f16700Schasinglulu void mt_cirq_clone_gic(void); 94*91f16700Schasinglulu void mt_cirq_enable(void); 95*91f16700Schasinglulu void mt_cirq_flush(void); 96*91f16700Schasinglulu void mt_cirq_disable(void); 97*91f16700Schasinglulu void mt_irq_unmask_for_sleep_ex(uint32_t irq); 98*91f16700Schasinglulu void set_wakeup_sources(uint32_t *list, uint32_t num_of_events); 99*91f16700Schasinglulu void mt_cirq_sw_reset(void); 100*91f16700Schasinglulu 101*91f16700Schasinglulu struct cirq_reg { 102*91f16700Schasinglulu uint32_t reg_num; 103*91f16700Schasinglulu uint32_t used; 104*91f16700Schasinglulu uint32_t mask; 105*91f16700Schasinglulu uint32_t pol; 106*91f16700Schasinglulu uint32_t sen; 107*91f16700Schasinglulu uint32_t pending; 108*91f16700Schasinglulu uint32_t the_link; 109*91f16700Schasinglulu }; 110*91f16700Schasinglulu 111*91f16700Schasinglulu struct cirq_events { 112*91f16700Schasinglulu uint32_t num_reg; 113*91f16700Schasinglulu uint32_t spi_start; 114*91f16700Schasinglulu uint32_t num_of_events; 115*91f16700Schasinglulu uint32_t *wakeup_events; 116*91f16700Schasinglulu struct cirq_reg table[CIRQ_REG_NUM]; 117*91f16700Schasinglulu uint32_t dist_base; 118*91f16700Schasinglulu uint32_t cirq_base; 119*91f16700Schasinglulu uint32_t used_reg_head; 120*91f16700Schasinglulu }; 121*91f16700Schasinglulu 122*91f16700Schasinglulu #endif /* PLAT_MT_CIRQ_H */ 123