xref: /arm-trusted-firmware/plat/mediatek/drivers/audio/mt8188/audio_domain.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2022, Mediatek Inc. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #include <errno.h>
8*91f16700Schasinglulu #include <common/debug.h>
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #include <audio.h>
11*91f16700Schasinglulu #include <mt_audio_private.h>
12*91f16700Schasinglulu #include <mtk_mmap_pool.h>
13*91f16700Schasinglulu #include <platform_def.h>
14*91f16700Schasinglulu #include <spm_reg.h>
15*91f16700Schasinglulu 
16*91f16700Schasinglulu #define MODULE_TAG "[AUDIO_DOMAIN]"
17*91f16700Schasinglulu 
18*91f16700Schasinglulu int32_t set_audio_domain_sidebands(void)
19*91f16700Schasinglulu {
20*91f16700Schasinglulu 	uint32_t val = mmio_read_32(PWR_STATUS);
21*91f16700Schasinglulu 
22*91f16700Schasinglulu 	if ((val & BIT(SPM_PWR_STATUS_AUDIO_BIT)) == 0) {
23*91f16700Schasinglulu 		ERROR("%s: %s, pwr_status=0x%x, w/o [%d]AUDIO!\n",
24*91f16700Schasinglulu 		      MODULE_TAG, __func__, val, SPM_PWR_STATUS_AUDIO_BIT);
25*91f16700Schasinglulu 		return -EIO;
26*91f16700Schasinglulu 	}
27*91f16700Schasinglulu 
28*91f16700Schasinglulu 	mmio_write_32(AFE_SE_SECURE_CON, 0x0);
29*91f16700Schasinglulu 
30*91f16700Schasinglulu 	mmio_write_32(AFE_SECURE_SIDEBAND0, 0x0);
31*91f16700Schasinglulu 	mmio_write_32(AFE_SECURE_SIDEBAND1, 0x0);
32*91f16700Schasinglulu 	mmio_write_32(AFE_SECURE_SIDEBAND2, 0x0);
33*91f16700Schasinglulu 	mmio_write_32(AFE_SECURE_SIDEBAND3, 0x0);
34*91f16700Schasinglulu 
35*91f16700Schasinglulu 	VERBOSE("%s: %s, SE_SECURE_CON=0x%x, SIDEBAND0/1/2/3=0x%x/0x%x/0x%x/0x%x\n",
36*91f16700Schasinglulu 		MODULE_TAG, __func__,
37*91f16700Schasinglulu 		mmio_read_32(AFE_SE_SECURE_CON),
38*91f16700Schasinglulu 		mmio_read_32(AFE_SECURE_SIDEBAND0),
39*91f16700Schasinglulu 		mmio_read_32(AFE_SECURE_SIDEBAND1),
40*91f16700Schasinglulu 		mmio_read_32(AFE_SECURE_SIDEBAND2),
41*91f16700Schasinglulu 		mmio_read_32(AFE_SECURE_SIDEBAND3));
42*91f16700Schasinglulu 
43*91f16700Schasinglulu 	return 0;
44*91f16700Schasinglulu }
45