1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, MediaTek Inc. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef APUSYS_DEVAPC_DEF_H 8*91f16700Schasinglulu #define APUSYS_DEVAPC_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include "../devapc/apusys_dapc_v1.h" 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* NoC */ 14*91f16700Schasinglulu #define SLAVE_MD32_SRAM SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* Control */ 17*91f16700Schasinglulu #define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 18*91f16700Schasinglulu #define SLAVE_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT 19*91f16700Schasinglulu #define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 20*91f16700Schasinglulu #define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 21*91f16700Schasinglulu #define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT 22*91f16700Schasinglulu #define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 23*91f16700Schasinglulu #define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 24*91f16700Schasinglulu #define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 25*91f16700Schasinglulu #define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 26*91f16700Schasinglulu #define SLAVE_ARE2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 27*91f16700Schasinglulu #define SLAVE_UNKNOWN SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 28*91f16700Schasinglulu #define SLAVE_APU_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 29*91f16700Schasinglulu #define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 30*91f16700Schasinglulu #define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 31*91f16700Schasinglulu #define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 32*91f16700Schasinglulu #define SLAVE_RCX_ACX_BULK SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 33*91f16700Schasinglulu #define SLAVE_ACX0_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 34*91f16700Schasinglulu #define SLAVE_RPCTOP_LITE_ACX0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 35*91f16700Schasinglulu #define SLAVE_ACX1_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 36*91f16700Schasinglulu #define SLAVE_RPCTOP_LITE_ACX1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 37*91f16700Schasinglulu #define SLAVE_RCX_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 38*91f16700Schasinglulu #define SLAVE_RCX_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 39*91f16700Schasinglulu #define SLAVE_SAE_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 40*91f16700Schasinglulu #define SLAVE_SAE_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 41*91f16700Schasinglulu #define SLAVE_RCX_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 42*91f16700Schasinglulu #define SLAVE_RCX_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 43*91f16700Schasinglulu #define SLAVE_SAE_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 44*91f16700Schasinglulu #define SLAVE_SAE_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 45*91f16700Schasinglulu #define SLAVE_MD32_SYSCTRL0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 46*91f16700Schasinglulu #define SLAVE_MD32_SYSCTRL1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT 47*91f16700Schasinglulu #define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 48*91f16700Schasinglulu #define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 49*91f16700Schasinglulu #define SLAVE_NOC_AXI SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 50*91f16700Schasinglulu #define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 51*91f16700Schasinglulu #define SLAVE_DBG_CRTL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 52*91f16700Schasinglulu #define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 53*91f16700Schasinglulu #define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 54*91f16700Schasinglulu #define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 55*91f16700Schasinglulu #define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 56*91f16700Schasinglulu #define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 57*91f16700Schasinglulu #define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT 58*91f16700Schasinglulu #define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 59*91f16700Schasinglulu #define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 60*91f16700Schasinglulu #define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 61*91f16700Schasinglulu #define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 62*91f16700Schasinglulu #define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 63*91f16700Schasinglulu #define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 64*91f16700Schasinglulu #define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 65*91f16700Schasinglulu #define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 66*91f16700Schasinglulu #define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 67*91f16700Schasinglulu #define SLAVE_CFG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT 68*91f16700Schasinglulu #define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 69*91f16700Schasinglulu #define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 70*91f16700Schasinglulu #define SLAVE_LOG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT 71*91f16700Schasinglulu #define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 72*91f16700Schasinglulu #define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 73*91f16700Schasinglulu #define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 74*91f16700Schasinglulu #define SLAVE_DFD_REG_SOC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 75*91f16700Schasinglulu #define SLAVE_SENSOR_WRAP_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 76*91f16700Schasinglulu #define SLAVE_SENSOR_WRAP_ACX0_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 77*91f16700Schasinglulu #define SLAVE_SENSOR_WRAP_ACX0_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 78*91f16700Schasinglulu #define SLAVE_SENSOR_WRAP_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 79*91f16700Schasinglulu #define SLAVE_SENSOR_WRAP_ACX1_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 80*91f16700Schasinglulu #define SLAVE_SENSOR_WRAP_ACX1_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 81*91f16700Schasinglulu #define SLAVE_REVISER SLAVE_FORBID_EXCEPT_D0_SEC_RW 82*91f16700Schasinglulu #define SLAVE_NOC SLAVE_FORBID_EXCEPT_D0_SEC_RW 83*91f16700Schasinglulu #define SLAVE_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 84*91f16700Schasinglulu #define SLAVE_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 85*91f16700Schasinglulu #define SLAVE_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 86*91f16700Schasinglulu #define SLAVE_NOC_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 87*91f16700Schasinglulu #define SLAVE_NOC_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 88*91f16700Schasinglulu #define SLAVE_NOC_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 89*91f16700Schasinglulu #define SLAVE_ACS SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT 90*91f16700Schasinglulu #define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_NO_PROTECT 91*91f16700Schasinglulu 92*91f16700Schasinglulu 93*91f16700Schasinglulu /* Power Domain: AO */ 94*91f16700Schasinglulu #define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16) 95*91f16700Schasinglulu #define APU_CTRL_DAPC_AO_DOM_NUM (16) 96*91f16700Schasinglulu #define APU_CTRL_DAPC_AO_SLAVE_NUM (30) 97*91f16700Schasinglulu #define DEVAPC_MASK (0x3U) 98*91f16700Schasinglulu #define DEVAPC_DOM_SHIFT (2) 99*91f16700Schasinglulu 100*91f16700Schasinglulu /* Power Domain: RCX */ 101*91f16700Schasinglulu #define APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16) 102*91f16700Schasinglulu #define APU_CTRL_DAPC_RCX_DOM_NUM (16) 103*91f16700Schasinglulu #define APU_CTRL_DAPC_RCX_SLAVE_NUM (63) 104*91f16700Schasinglulu 105*91f16700Schasinglulu #define APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16) 106*91f16700Schasinglulu #define APU_NOC_DAPC_RCX_DOM_NUM (16) 107*91f16700Schasinglulu #define APU_NOC_DAPC_RCX_SLAVE_NUM (5) 108*91f16700Schasinglulu 109*91f16700Schasinglulu #endif /* APUSYS_DEVAPC_DEF_H */ 110