1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef MSS_MEM_H 9*91f16700Schasinglulu #define MSS_MEM_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu /* MSS SRAM Memory base */ 12*91f16700Schasinglulu #define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000) 13*91f16700Schasinglulu 14*91f16700Schasinglulu enum mss_pm_ctrl_handshake { 15*91f16700Schasinglulu MSS_UN_INITIALIZED = 0, 16*91f16700Schasinglulu MSS_COMPATIBILITY_ERROR = 1, 17*91f16700Schasinglulu MSS_ACKNOWLEDGMENT = 2, 18*91f16700Schasinglulu HOST_ACKNOWLEDGMENT = 3 19*91f16700Schasinglulu }; 20*91f16700Schasinglulu 21*91f16700Schasinglulu enum mss_pm_ctrl_rtos_env { 22*91f16700Schasinglulu MSS_MULTI_PROCESS_ENV = 0, 23*91f16700Schasinglulu MSS_SINGLE_PROCESS_ENV = 1, 24*91f16700Schasinglulu MSS_MAX_PROCESS_ENV 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu 27*91f16700Schasinglulu struct mss_pm_ctrl_block { 28*91f16700Schasinglulu /* This field is used to synchronize the Host 29*91f16700Schasinglulu * and MSS initialization sequence 30*91f16700Schasinglulu * Valid Values 31*91f16700Schasinglulu * 0 - Un-Initialized 32*91f16700Schasinglulu * 1 - Compatibility Error 33*91f16700Schasinglulu * 2 - MSS Acknowledgment 34*91f16700Schasinglulu * 3 - Host Acknowledgment 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu unsigned int handshake; 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* 39*91f16700Schasinglulu * This field include Host IPC version. Once received by the MSS 40*91f16700Schasinglulu * It will be compared to MSS IPC version and set MSS Acknowledge to 41*91f16700Schasinglulu * "compatibility error" in case there is no match 42*91f16700Schasinglulu */ 43*91f16700Schasinglulu unsigned int ipc_version; 44*91f16700Schasinglulu unsigned int ipc_base_address; 45*91f16700Schasinglulu unsigned int ipc_state; 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* Following fields defines firmware core architecture */ 48*91f16700Schasinglulu unsigned int num_of_cores; 49*91f16700Schasinglulu unsigned int num_of_clusters; 50*91f16700Schasinglulu unsigned int num_of_cores_per_cluster; 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* Following fields define pm trace debug base address */ 53*91f16700Schasinglulu unsigned int pm_trace_ctrl_base_address; 54*91f16700Schasinglulu unsigned int pm_trace_info_base_address; 55*91f16700Schasinglulu unsigned int pm_trace_info_core_size; 56*91f16700Schasinglulu 57*91f16700Schasinglulu unsigned int ctrl_blk_size; 58*91f16700Schasinglulu }; 59*91f16700Schasinglulu 60*91f16700Schasinglulu #endif /* MSS_MEM_H */ 61