1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <assert.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <lib/psci/psci.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <marvell_pm.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */ 16*91f16700Schasinglulu extern const plat_psci_ops_t plat_arm_psci_pm_ops; 17*91f16700Schasinglulu 18*91f16700Schasinglulu /***************************************************************************** 19*91f16700Schasinglulu * Private function to program the mailbox for a cpu before it is released 20*91f16700Schasinglulu * from reset. This function assumes that the mail box base is within 21*91f16700Schasinglulu * the MARVELL_SHARED_RAM region 22*91f16700Schasinglulu ***************************************************************************** 23*91f16700Schasinglulu */ 24*91f16700Schasinglulu void marvell_program_mailbox(uintptr_t address) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* 29*91f16700Schasinglulu * Ensure that the PLAT_MARVELL_MAILBOX_BASE is within 30*91f16700Schasinglulu * MARVELL_SHARED_RAM region. 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu assert((PLAT_MARVELL_MAILBOX_BASE >= MARVELL_SHARED_RAM_BASE) && 33*91f16700Schasinglulu ((PLAT_MARVELL_MAILBOX_BASE + sizeof(*mailbox)) <= 34*91f16700Schasinglulu (MARVELL_SHARED_RAM_BASE + MARVELL_SHARED_RAM_SIZE))); 35*91f16700Schasinglulu 36*91f16700Schasinglulu mailbox[MBOX_IDX_MAGIC] = MVEBU_MAILBOX_MAGIC_NUM; 37*91f16700Schasinglulu mailbox[MBOX_IDX_SEC_ADDR] = address; 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Flush data cache if the mail box shared RAM is cached */ 40*91f16700Schasinglulu #if PLAT_MARVELL_SHARED_RAM_CACHED 41*91f16700Schasinglulu flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE + 42*91f16700Schasinglulu 8 * MBOX_IDX_MAGIC, 43*91f16700Schasinglulu 2 * sizeof(uint64_t)); 44*91f16700Schasinglulu #endif 45*91f16700Schasinglulu } 46*91f16700Schasinglulu 47*91f16700Schasinglulu /***************************************************************************** 48*91f16700Schasinglulu * The ARM Standard platform definition of platform porting API 49*91f16700Schasinglulu * `plat_setup_psci_ops`. 50*91f16700Schasinglulu ***************************************************************************** 51*91f16700Schasinglulu */ 52*91f16700Schasinglulu int plat_setup_psci_ops(uintptr_t sec_entrypoint, 53*91f16700Schasinglulu const plat_psci_ops_t **psci_ops) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu *psci_ops = &plat_arm_psci_pm_ops; 56*91f16700Schasinglulu 57*91f16700Schasinglulu /* Setup mailbox with entry point. */ 58*91f16700Schasinglulu marvell_program_mailbox(sec_entrypoint); 59*91f16700Schasinglulu return 0; 60*91f16700Schasinglulu } 61