1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <assert.h> 9*91f16700Schasinglulu #include <string.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <arch_helpers.h> 14*91f16700Schasinglulu #include <common/bl_common.h> 15*91f16700Schasinglulu #include <common/debug.h> 16*91f16700Schasinglulu #include <common/desc_image_load.h> 17*91f16700Schasinglulu #include <drivers/console.h> 18*91f16700Schasinglulu #include <lib/utils.h> 19*91f16700Schasinglulu 20*91f16700Schasinglulu #ifdef SPD_opteed 21*91f16700Schasinglulu #include <optee_utils.h> 22*91f16700Schasinglulu #endif 23*91f16700Schasinglulu #include <marvell_def.h> 24*91f16700Schasinglulu #include <plat_marvell.h> 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* Data structure which holds the extents of the trusted SRAM for BL2 */ 27*91f16700Schasinglulu static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* Weak definitions may be overridden in specific MARVELL standard platform */ 30*91f16700Schasinglulu #pragma weak bl2_early_platform_setup2 31*91f16700Schasinglulu #pragma weak bl2_platform_setup 32*91f16700Schasinglulu #pragma weak bl2_plat_arch_setup 33*91f16700Schasinglulu #pragma weak bl2_plat_sec_mem_layout 34*91f16700Schasinglulu 35*91f16700Schasinglulu meminfo_t *bl2_plat_sec_mem_layout(void) 36*91f16700Schasinglulu { 37*91f16700Schasinglulu return &bl2_tzram_layout; 38*91f16700Schasinglulu } 39*91f16700Schasinglulu 40*91f16700Schasinglulu /***************************************************************************** 41*91f16700Schasinglulu * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 42*91f16700Schasinglulu * in x0. This memory layout is sitting at the base of the free trusted SRAM. 43*91f16700Schasinglulu * Copy it to a safe location before its reclaimed by later BL2 functionality. 44*91f16700Schasinglulu ***************************************************************************** 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) 47*91f16700Schasinglulu { 48*91f16700Schasinglulu /* Initialize the console to provide early debug support */ 49*91f16700Schasinglulu marvell_console_boot_init(); 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* Setup the BL2 memory layout */ 52*91f16700Schasinglulu bl2_tzram_layout = *mem_layout; 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* Initialise the IO layer and register platform IO devices */ 55*91f16700Schasinglulu plat_marvell_io_setup(); 56*91f16700Schasinglulu } 57*91f16700Schasinglulu 58*91f16700Schasinglulu 59*91f16700Schasinglulu void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, 60*91f16700Schasinglulu u_register_t arg2, u_register_t arg3) 61*91f16700Schasinglulu { 62*91f16700Schasinglulu struct meminfo *mem_layout = (struct meminfo *)arg1; 63*91f16700Schasinglulu 64*91f16700Schasinglulu marvell_bl2_early_platform_setup(mem_layout); 65*91f16700Schasinglulu } 66*91f16700Schasinglulu 67*91f16700Schasinglulu void bl2_platform_setup(void) 68*91f16700Schasinglulu { 69*91f16700Schasinglulu /* Nothing to do */ 70*91f16700Schasinglulu } 71*91f16700Schasinglulu 72*91f16700Schasinglulu /***************************************************************************** 73*91f16700Schasinglulu * Perform the very early platform specific architectural setup here. At the 74*91f16700Schasinglulu * moment this is only initializes the mmu in a quick and dirty way. 75*91f16700Schasinglulu ***************************************************************************** 76*91f16700Schasinglulu */ 77*91f16700Schasinglulu void marvell_bl2_plat_arch_setup(void) 78*91f16700Schasinglulu { 79*91f16700Schasinglulu marvell_setup_page_tables(bl2_tzram_layout.total_base, 80*91f16700Schasinglulu bl2_tzram_layout.total_size, 81*91f16700Schasinglulu BL_CODE_BASE, 82*91f16700Schasinglulu BL_CODE_END, 83*91f16700Schasinglulu BL_RO_DATA_BASE, 84*91f16700Schasinglulu BL_RO_DATA_END 85*91f16700Schasinglulu #if USE_COHERENT_MEM 86*91f16700Schasinglulu , BL_COHERENT_RAM_BASE, 87*91f16700Schasinglulu BL_COHERENT_RAM_END 88*91f16700Schasinglulu #endif 89*91f16700Schasinglulu ); 90*91f16700Schasinglulu enable_mmu_el1(0); 91*91f16700Schasinglulu } 92*91f16700Schasinglulu 93*91f16700Schasinglulu void bl2_plat_arch_setup(void) 94*91f16700Schasinglulu { 95*91f16700Schasinglulu marvell_bl2_plat_arch_setup(); 96*91f16700Schasinglulu } 97*91f16700Schasinglulu 98*91f16700Schasinglulu int marvell_bl2_handle_post_image_load(unsigned int image_id) 99*91f16700Schasinglulu { 100*91f16700Schasinglulu int err = 0; 101*91f16700Schasinglulu bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 102*91f16700Schasinglulu 103*91f16700Schasinglulu #ifdef SPD_opteed 104*91f16700Schasinglulu bl_mem_params_node_t *pager_mem_params = NULL; 105*91f16700Schasinglulu bl_mem_params_node_t *paged_mem_params = NULL; 106*91f16700Schasinglulu #endif /* SPD_opteed */ 107*91f16700Schasinglulu assert(bl_mem_params); 108*91f16700Schasinglulu 109*91f16700Schasinglulu switch (image_id) { 110*91f16700Schasinglulu case BL32_IMAGE_ID: 111*91f16700Schasinglulu #ifdef SPD_opteed 112*91f16700Schasinglulu pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 113*91f16700Schasinglulu assert(pager_mem_params); 114*91f16700Schasinglulu 115*91f16700Schasinglulu paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 116*91f16700Schasinglulu assert(paged_mem_params); 117*91f16700Schasinglulu 118*91f16700Schasinglulu err = parse_optee_header(&bl_mem_params->ep_info, 119*91f16700Schasinglulu &pager_mem_params->image_info, 120*91f16700Schasinglulu &paged_mem_params->image_info); 121*91f16700Schasinglulu if (err != 0) 122*91f16700Schasinglulu WARN("OPTEE header parse error.\n"); 123*91f16700Schasinglulu #endif /* SPD_opteed */ 124*91f16700Schasinglulu bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl32_entry(); 125*91f16700Schasinglulu break; 126*91f16700Schasinglulu 127*91f16700Schasinglulu case BL33_IMAGE_ID: 128*91f16700Schasinglulu /* BL33 expects to receive the primary CPU MPID (through r0) */ 129*91f16700Schasinglulu bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 130*91f16700Schasinglulu bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl33_entry(); 131*91f16700Schasinglulu break; 132*91f16700Schasinglulu #ifdef SCP_BL2_BASE 133*91f16700Schasinglulu case SCP_BL2_IMAGE_ID: 134*91f16700Schasinglulu /* The subsequent handling of SCP_BL2 is platform specific */ 135*91f16700Schasinglulu err = bl2_plat_handle_scp_bl2(&bl_mem_params->image_info); 136*91f16700Schasinglulu if (err) { 137*91f16700Schasinglulu WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 138*91f16700Schasinglulu } 139*91f16700Schasinglulu break; 140*91f16700Schasinglulu #endif 141*91f16700Schasinglulu default: 142*91f16700Schasinglulu /* Do nothing in default case */ 143*91f16700Schasinglulu break; 144*91f16700Schasinglulu } 145*91f16700Schasinglulu 146*91f16700Schasinglulu return err; 147*91f16700Schasinglulu 148*91f16700Schasinglulu } 149*91f16700Schasinglulu 150*91f16700Schasinglulu /******************************************************************************* 151*91f16700Schasinglulu * This function can be used by the platforms to update/use image 152*91f16700Schasinglulu * information for given `image_id`. 153*91f16700Schasinglulu ******************************************************************************/ 154*91f16700Schasinglulu int bl2_plat_handle_post_image_load(unsigned int image_id) 155*91f16700Schasinglulu { 156*91f16700Schasinglulu return marvell_bl2_handle_post_image_load(image_id); 157*91f16700Schasinglulu } 158*91f16700Schasinglulu 159