xref: /arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/mss_pm_ipc.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (C) 2018 Marvell International Ltd.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier:     BSD-3-Clause
5*91f16700Schasinglulu  * https://spdx.org/licenses
6*91f16700Schasinglulu  */
7*91f16700Schasinglulu 
8*91f16700Schasinglulu #ifndef MSS_PM_IPC_H
9*91f16700Schasinglulu #define MSS_PM_IPC_H
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #include <mss_ipc_drv.h>
12*91f16700Schasinglulu 
13*91f16700Schasinglulu /* Currently MSS does not support Cluster level Power Down */
14*91f16700Schasinglulu #define DISABLE_CLUSTER_LEVEL
15*91f16700Schasinglulu 
16*91f16700Schasinglulu 
17*91f16700Schasinglulu /*****************************************************************************
18*91f16700Schasinglulu  * mss_pm_ipc_msg_send
19*91f16700Schasinglulu  *
20*91f16700Schasinglulu  * DESCRIPTION: create and transmit IPC message
21*91f16700Schasinglulu  *****************************************************************************
22*91f16700Schasinglulu  */
23*91f16700Schasinglulu int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id,
24*91f16700Schasinglulu 			const psci_power_state_t *target_state);
25*91f16700Schasinglulu 
26*91f16700Schasinglulu /*****************************************************************************
27*91f16700Schasinglulu  * mss_pm_ipc_msg_trigger
28*91f16700Schasinglulu  *
29*91f16700Schasinglulu  * DESCRIPTION: Trigger IPC message interrupt to MSS
30*91f16700Schasinglulu  *****************************************************************************
31*91f16700Schasinglulu  */
32*91f16700Schasinglulu int mss_pm_ipc_msg_trigger(void);
33*91f16700Schasinglulu 
34*91f16700Schasinglulu 
35*91f16700Schasinglulu #endif /* MSS_PM_IPC_H */
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