1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2021 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef MSS_DEFS_H 9*91f16700Schasinglulu #define MSS_DEFS_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define MSS_DMA_SRCBR(base) (base + 0xC0) 12*91f16700Schasinglulu #define MSS_DMA_DSTBR(base) (base + 0xC4) 13*91f16700Schasinglulu #define MSS_DMA_CTRLR(base) (base + 0xC8) 14*91f16700Schasinglulu #define MSS_M3_RSTCR(base) (base + 0xFC) 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define MSS_DMA_CTRLR_SIZE_OFFSET (0) 17*91f16700Schasinglulu #define MSS_DMA_CTRLR_REQ_OFFSET (15) 18*91f16700Schasinglulu #define MSS_DMA_CTRLR_REQ_SET (1) 19*91f16700Schasinglulu #define MSS_DMA_CTRLR_ACK_OFFSET (12) 20*91f16700Schasinglulu #define MSS_DMA_CTRLR_ACK_MASK (0x1) 21*91f16700Schasinglulu #define MSS_DMA_CTRLR_ACK_READY (1) 22*91f16700Schasinglulu #define MSS_M3_RSTCR_RST_OFFSET (0) 23*91f16700Schasinglulu #define MSS_M3_RSTCR_RST_OFF (1) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define MSS_FW_READY_MAGIC 0x46575144 /* FWRD */ 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define MSS_AP_REGS_OFFSET 0x00580000 28*91f16700Schasinglulu #define MSS_CP_SRAM_OFFSET 0x00220000 29*91f16700Schasinglulu #define MSS_CP_REGS_OFFSET 0x00280000 30*91f16700Schasinglulu 31*91f16700Schasinglulu void mss_start_cp_cm3(int cp); 32*91f16700Schasinglulu 33*91f16700Schasinglulu #endif /* MSS_DEFS_H */ 34