1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2021 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <platform_def.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <common/bl_common.h> 11*91f16700Schasinglulu #include <common/debug.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #include <armada_common.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #include "mss_defs.h" 17*91f16700Schasinglulu 18*91f16700Schasinglulu void mss_start_cp_cm3(int cp) 19*91f16700Schasinglulu { 20*91f16700Schasinglulu uint32_t magic; 21*91f16700Schasinglulu uintptr_t sram = MVEBU_CP_REGS_BASE(cp) + MSS_CP_SRAM_OFFSET; 22*91f16700Schasinglulu uintptr_t regs = MVEBU_CP_REGS_BASE(cp) + MSS_CP_REGS_OFFSET; 23*91f16700Schasinglulu 24*91f16700Schasinglulu magic = mmio_read_32(sram); 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* Make sure the FW was loaded */ 27*91f16700Schasinglulu if (magic != MSS_FW_READY_MAGIC) { 28*91f16700Schasinglulu return; 29*91f16700Schasinglulu } 30*91f16700Schasinglulu 31*91f16700Schasinglulu NOTICE("Starting CP%d MSS CPU\n", cp); 32*91f16700Schasinglulu /* remove the magic */ 33*91f16700Schasinglulu mmio_write_32(sram, 0); 34*91f16700Schasinglulu /* Release M3 from reset */ 35*91f16700Schasinglulu mmio_write_32(MSS_M3_RSTCR(regs), 36*91f16700Schasinglulu (MSS_M3_RSTCR_RST_OFF << MSS_M3_RSTCR_RST_OFFSET)); 37*91f16700Schasinglulu } 38