1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu#include <marvell_pm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 13*91f16700Schasinglulu .globl plat_get_my_entrypoint 14*91f16700Schasinglulu .globl plat_is_my_cpu_primary 15*91f16700Schasinglulu .globl plat_reset_handler 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* ----------------------------------------------------- 18*91f16700Schasinglulu * void plat_secondary_cold_boot_setup (void); 19*91f16700Schasinglulu * 20*91f16700Schasinglulu * This function performs any platform specific actions 21*91f16700Schasinglulu * needed for a secondary cpu after a cold reset. Right 22*91f16700Schasinglulu * now this is a stub function. 23*91f16700Schasinglulu * ----------------------------------------------------- 24*91f16700Schasinglulu */ 25*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 26*91f16700Schasinglulu mov x0, #0 27*91f16700Schasinglulu ret 28*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* --------------------------------------------------------------------- 31*91f16700Schasinglulu * unsigned long plat_get_my_entrypoint (void); 32*91f16700Schasinglulu * 33*91f16700Schasinglulu * Main job of this routine is to distinguish 34*91f16700Schasinglulu * between a cold and warm boot 35*91f16700Schasinglulu * For a cold boot, return 0. 36*91f16700Schasinglulu * For a warm boot, read the mailbox and return the address it contains. 37*91f16700Schasinglulu * 38*91f16700Schasinglulu * --------------------------------------------------------------------- 39*91f16700Schasinglulu */ 40*91f16700Schasinglulufunc plat_get_my_entrypoint 41*91f16700Schasinglulu /* Read first word and compare it with magic num */ 42*91f16700Schasinglulu mov_imm x0, PLAT_MARVELL_MAILBOX_BASE 43*91f16700Schasinglulu ldr x1, [x0] 44*91f16700Schasinglulu mov_imm x2, MVEBU_MAILBOX_MAGIC_NUM 45*91f16700Schasinglulu cmp x1, x2 46*91f16700Schasinglulu beq warm_boot /* If compare failed, return 0, i.e. cold boot */ 47*91f16700Schasinglulu mov x0, #0 48*91f16700Schasinglulu ret 49*91f16700Schasingluluwarm_boot: 50*91f16700Schasinglulu mov_imm x1, MBOX_IDX_SEC_ADDR /* Get the jump address */ 51*91f16700Schasinglulu subs x1, x1, #1 52*91f16700Schasinglulu mov x2, #(MBOX_IDX_SEC_ADDR * 8) 53*91f16700Schasinglulu lsl x3, x2, x1 54*91f16700Schasinglulu add x0, x0, x3 55*91f16700Schasinglulu ldr x0, [x0] 56*91f16700Schasinglulu ret 57*91f16700Schasingluluendfunc plat_get_my_entrypoint 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* ----------------------------------------------------- 60*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary (void); 61*91f16700Schasinglulu * 62*91f16700Schasinglulu * Find out whether the current cpu is the primary 63*91f16700Schasinglulu * cpu. 64*91f16700Schasinglulu * ----------------------------------------------------- 65*91f16700Schasinglulu */ 66*91f16700Schasinglulufunc plat_is_my_cpu_primary 67*91f16700Schasinglulu mrs x0, mpidr_el1 68*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 69*91f16700Schasinglulu cmp x0, #MVEBU_PRIMARY_CPU 70*91f16700Schasinglulu cset w0, eq 71*91f16700Schasinglulu ret 72*91f16700Schasingluluendfunc plat_is_my_cpu_primary 73*91f16700Schasinglulu 74*91f16700Schasinglulu /* ----------------------------------------------------- 75*91f16700Schasinglulu * void plat_reset_handler (void); 76*91f16700Schasinglulu * 77*91f16700Schasinglulu * Platform specific configuration right after cpu is 78*91f16700Schasinglulu * is our of reset. 79*91f16700Schasinglulu * 80*91f16700Schasinglulu * The plat_reset_handler can clobber x0 - x18, x30. 81*91f16700Schasinglulu * ----------------------------------------------------- 82*91f16700Schasinglulu */ 83*91f16700Schasinglulufunc plat_reset_handler 84*91f16700Schasinglulu /* 85*91f16700Schasinglulu * Note: the configurations below should be done before MMU, 86*91f16700Schasinglulu * I Cache and L2are enabled. 87*91f16700Schasinglulu * The reset handler is executed right after reset 88*91f16700Schasinglulu * and before Caches are enabled. 89*91f16700Schasinglulu */ 90*91f16700Schasinglulu 91*91f16700Schasinglulu /* Enable L1/L2 ECC and Parity */ 92*91f16700Schasinglulu mrs x5, s3_1_c11_c0_2 /* L2 Ctrl */ 93*91f16700Schasinglulu orr x5, x5, #(1 << 21) /* Enable L1/L2 cache ECC & Parity */ 94*91f16700Schasinglulu msr s3_1_c11_c0_2, x5 /* L2 Ctrl */ 95*91f16700Schasinglulu 96*91f16700Schasinglulu#if LLC_ENABLE 97*91f16700Schasinglulu /* 98*91f16700Schasinglulu * Enable L2 UniqueClean evictions 99*91f16700Schasinglulu * Note: this configuration assumes that LLC is configured 100*91f16700Schasinglulu * in exclusive mode. 101*91f16700Schasinglulu * Later on in the code this assumption will be validated 102*91f16700Schasinglulu */ 103*91f16700Schasinglulu mrs x5, s3_1_c15_c0_0 /* L2 Ctrl */ 104*91f16700Schasinglulu orr x5, x5, #(1 << 14) /* Enable UniqueClean evictions with data */ 105*91f16700Schasinglulu msr s3_1_c15_c0_0, x5 /* L2 Ctrl */ 106*91f16700Schasinglulu#endif 107*91f16700Schasinglulu 108*91f16700Schasinglulu /* Instruction Barrier to allow msr command completion */ 109*91f16700Schasinglulu isb 110*91f16700Schasinglulu 111*91f16700Schasinglulu ret 112*91f16700Schasingluluendfunc plat_reset_handler 113