1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <plat_marvell.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu 11*91f16700Schasinglulu /* MMU entry for internal (register) space access */ 12*91f16700Schasinglulu #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 13*91f16700Schasinglulu DEVICE0_SIZE, \ 14*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* 17*91f16700Schasinglulu * Table of regions for various BL stages to map using the MMU. 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu #if IMAGE_BL1 20*91f16700Schasinglulu const mmap_region_t plat_marvell_mmap[] = { 21*91f16700Schasinglulu MARVELL_MAP_SECURE_RAM, 22*91f16700Schasinglulu MAP_DEVICE0, 23*91f16700Schasinglulu {0} 24*91f16700Schasinglulu }; 25*91f16700Schasinglulu #endif 26*91f16700Schasinglulu #if IMAGE_BL2 27*91f16700Schasinglulu const mmap_region_t plat_marvell_mmap[] = { 28*91f16700Schasinglulu MARVELL_MAP_SECURE_RAM, 29*91f16700Schasinglulu MAP_DEVICE0, 30*91f16700Schasinglulu MARVELL_MAP_DRAM, 31*91f16700Schasinglulu #ifdef SPD_opteed 32*91f16700Schasinglulu MARVELL_MAP_OPTEE_CORE_MEM, 33*91f16700Schasinglulu MARVELL_OPTEE_PAGEABLE_LOAD_MEM, 34*91f16700Schasinglulu #endif 35*91f16700Schasinglulu {0} 36*91f16700Schasinglulu }; 37*91f16700Schasinglulu #endif 38*91f16700Schasinglulu 39*91f16700Schasinglulu #if IMAGE_BL2U 40*91f16700Schasinglulu const mmap_region_t plat_marvell_mmap[] = { 41*91f16700Schasinglulu MARVELL_MAP_SECURE_RAM, 42*91f16700Schasinglulu MAP_DEVICE0, 43*91f16700Schasinglulu {0} 44*91f16700Schasinglulu }; 45*91f16700Schasinglulu #endif 46*91f16700Schasinglulu 47*91f16700Schasinglulu #if IMAGE_BLE 48*91f16700Schasinglulu const mmap_region_t plat_marvell_mmap[] = { 49*91f16700Schasinglulu MAP_DEVICE0, 50*91f16700Schasinglulu {0} 51*91f16700Schasinglulu }; 52*91f16700Schasinglulu #endif 53*91f16700Schasinglulu 54*91f16700Schasinglulu #if IMAGE_BL31 55*91f16700Schasinglulu const mmap_region_t plat_marvell_mmap[] = { 56*91f16700Schasinglulu MARVELL_MAP_SECURE_RAM, 57*91f16700Schasinglulu MAP_DEVICE0, 58*91f16700Schasinglulu MARVELL_MAP_DRAM, 59*91f16700Schasinglulu {0} 60*91f16700Schasinglulu }; 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu #if IMAGE_BL32 63*91f16700Schasinglulu const mmap_region_t plat_marvell_mmap[] = { 64*91f16700Schasinglulu MARVELL_MAP_SECURE_RAM, 65*91f16700Schasinglulu MAP_DEVICE0, 66*91f16700Schasinglulu {0} 67*91f16700Schasinglulu }; 68*91f16700Schasinglulu #endif 69*91f16700Schasinglulu 70*91f16700Schasinglulu MARVELL_CASSERT_MMAP; 71