xref: /arm-trusted-firmware/plat/marvell/armada/a8k/a70x0_mochabin/board/phy-porting-layer.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (C) 2021 Sartura Ltd.
3*91f16700Schasinglulu  * Copyright (C) 2021 Globalscale technologies, Inc.
4*91f16700Schasinglulu  * Copyright (C) 2021 Marvell International Ltd.
5*91f16700Schasinglulu  *
6*91f16700Schasinglulu  * SPDX-License-Identifier:     BSD-3-Clause
7*91f16700Schasinglulu  * https://spdx.org/licenses
8*91f16700Schasinglulu  */
9*91f16700Schasinglulu 
10*91f16700Schasinglulu #ifndef __PHY_PORTING_LAYER_H
11*91f16700Schasinglulu #define __PHY_PORTING_LAYER_H
12*91f16700Schasinglulu 
13*91f16700Schasinglulu #define MAX_LANE_NR		6
14*91f16700Schasinglulu 
15*91f16700Schasinglulu static const struct xfi_params
16*91f16700Schasinglulu 	xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
17*91f16700Schasinglulu 	/* AP0 */
18*91f16700Schasinglulu 	{
19*91f16700Schasinglulu 		/* CP 0 */
20*91f16700Schasinglulu 		{
21*91f16700Schasinglulu 			{ 0 }, /* Comphy0 */
22*91f16700Schasinglulu 			{ 0 }, /* Comphy1 */
23*91f16700Schasinglulu 			{ 0 }, /* Comphy2 */
24*91f16700Schasinglulu 			{ 0 }, /* Comphy3 */
25*91f16700Schasinglulu 			{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x60,
26*91f16700Schasinglulu 			  .g1_dfe_res = 0x1, .g1_amp = 0x1c, .g1_emph = 0xe,
27*91f16700Schasinglulu 			  .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
28*91f16700Schasinglulu 			  .g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
29*91f16700Schasinglulu 			  .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
30*91f16700Schasinglulu 			  .valid = 1 }, /* Comphy4 */
31*91f16700Schasinglulu 			{ 0 }, /* Comphy5 */
32*91f16700Schasinglulu 		},
33*91f16700Schasinglulu 	},
34*91f16700Schasinglulu };
35*91f16700Schasinglulu 
36*91f16700Schasinglulu static const struct sata_params
37*91f16700Schasinglulu 	sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
38*91f16700Schasinglulu 	/* AP0 */
39*91f16700Schasinglulu 	{
40*91f16700Schasinglulu 		/* CP 0 */
41*91f16700Schasinglulu 		{
42*91f16700Schasinglulu 			{ 0 }, /* Comphy0 */
43*91f16700Schasinglulu 			{ 0 }, /* Comphy1 */
44*91f16700Schasinglulu 			{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
45*91f16700Schasinglulu 			  .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
46*91f16700Schasinglulu 			  .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
47*91f16700Schasinglulu 			  .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
48*91f16700Schasinglulu 			  .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
49*91f16700Schasinglulu 			  .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
50*91f16700Schasinglulu 			  .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
51*91f16700Schasinglulu 			  .align90 = 0x61,
52*91f16700Schasinglulu 			  .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
53*91f16700Schasinglulu 			  .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
54*91f16700Schasinglulu 			  .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
55*91f16700Schasinglulu 			  .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
56*91f16700Schasinglulu 			  .polarity_invert = COMPHY_POLARITY_NO_INVERT,
57*91f16700Schasinglulu 			  .valid = 0x1
58*91f16700Schasinglulu 			}, /* Comphy2 */
59*91f16700Schasinglulu 			{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
60*91f16700Schasinglulu 			  .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
61*91f16700Schasinglulu 			  .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
62*91f16700Schasinglulu 			  .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
63*91f16700Schasinglulu 			  .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
64*91f16700Schasinglulu 			  .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
65*91f16700Schasinglulu 			  .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
66*91f16700Schasinglulu 			  .align90 = 0x61,
67*91f16700Schasinglulu 			  .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
68*91f16700Schasinglulu 			  .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
69*91f16700Schasinglulu 			  .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
70*91f16700Schasinglulu 			  .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
71*91f16700Schasinglulu 			  .polarity_invert = COMPHY_POLARITY_NO_INVERT,
72*91f16700Schasinglulu 			  .valid = 0x1
73*91f16700Schasinglulu 			}, /* Comphy3 */
74*91f16700Schasinglulu 			{ 0 }, /* Comphy4 */
75*91f16700Schasinglulu 			{ 0 }, /* Comphy5 */
76*91f16700Schasinglulu 		},
77*91f16700Schasinglulu 	},
78*91f16700Schasinglulu };
79*91f16700Schasinglulu 
80*91f16700Schasinglulu static const struct usb_params
81*91f16700Schasinglulu 	usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
82*91f16700Schasinglulu 	[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
83*91f16700Schasinglulu 		.polarity_invert = COMPHY_POLARITY_NO_INVERT
84*91f16700Schasinglulu 	},
85*91f16700Schasinglulu };
86*91f16700Schasinglulu 
87*91f16700Schasinglulu #endif /* __PHY_PORTING_LAYER_H */
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