1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #include <armada_common.h> 9 10 /* 11 * If bootrom is currently at BLE there's no need to include the memory 12 * maps structure at this point 13 */ 14 #include <mvebu_def.h> 15 #ifndef IMAGE_BLE 16 17 /***************************************************************************** 18 * AMB Configuration 19 ***************************************************************************** 20 */ 21 struct addr_map_win *amb_memory_map; 22 23 int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, 24 uintptr_t base) 25 { 26 *win = amb_memory_map; 27 if (*win == NULL) 28 *size = 0; 29 else 30 *size = ARRAY_SIZE(amb_memory_map); 31 32 return 0; 33 } 34 #endif 35 36 /***************************************************************************** 37 * IO WIN Configuration 38 ***************************************************************************** 39 */ 40 struct addr_map_win io_win_memory_map[] = { 41 #ifndef IMAGE_BLE 42 /* MCI 0 indirect window */ 43 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID}, 44 /* MCI 1 indirect window */ 45 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID}, 46 #endif 47 }; 48 49 uint32_t marvell_get_io_win_gcr_target(int ap_index) 50 { 51 return PIDI_TID; 52 } 53 54 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, 55 uint32_t *size) 56 { 57 *win = io_win_memory_map; 58 if (*win == NULL) 59 *size = 0; 60 else 61 *size = ARRAY_SIZE(io_win_memory_map); 62 63 return 0; 64 } 65 66 #ifndef IMAGE_BLE 67 /***************************************************************************** 68 * IOB Configuration 69 ***************************************************************************** 70 */ 71 struct addr_map_win iob_memory_map[] = { 72 /* PEX0_X4 window */ 73 {0x00000000f6000000, 0x6000000, PEX0_TID}, 74 {0x00000000c0000000, 0x30000000, PEX0_TID}, 75 {0x0000000800000000, 0x200000000, PEX0_TID}, 76 }; 77 78 int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, 79 uintptr_t base) 80 { 81 *win = iob_memory_map; 82 *size = ARRAY_SIZE(iob_memory_map); 83 84 return 0; 85 } 86 #endif 87 88 /***************************************************************************** 89 * CCU Configuration 90 ***************************************************************************** 91 */ 92 struct addr_map_win ccu_memory_map[] = { 93 #ifdef IMAGE_BLE 94 {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ 95 #else 96 #if LLC_SRAM 97 /* This entry is prepared for OP-TEE OS that enables the LLC SRAM 98 * and changes the window target to SRAM_TID. 99 */ 100 {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, 101 #endif 102 {0x00000000f2000000, 0xe000000, IO_0_TID}, 103 {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ 104 {0x0000000800000000, 0x200000000, IO_0_TID}, /* IO window */ 105 #endif 106 }; 107 108 uint32_t marvell_get_ccu_gcr_target(int ap) 109 { 110 return DRAM_0_TID; 111 } 112 113 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, 114 uint32_t *size) 115 { 116 *win = ccu_memory_map; 117 *size = ARRAY_SIZE(ccu_memory_map); 118 119 return 0; 120 } 121 122 #ifdef IMAGE_BLE 123 124 struct pci_hw_cfg *plat_get_pcie_hw_data(void) 125 { 126 return NULL; 127 } 128 129 /***************************************************************************** 130 * SKIP IMAGE Configuration 131 ***************************************************************************** 132 */ 133 #if PLAT_RECOVERY_IMAGE_ENABLE 134 struct skip_image skip_im = { 135 .detection_method = GPIO, 136 .info.gpio.num = 33, 137 .info.gpio.button_state = HIGH, 138 .info.test.cp_ap = CP, 139 .info.test.cp_index = 0, 140 }; 141 142 void *plat_marvell_get_skip_image_data(void) 143 { 144 /* Return the skip_image configurations */ 145 return &skip_im; 146 } 147 #endif 148 #endif 149