1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2021 Marek Behun <marek.behun@nic.cz> 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * Based on plat/marvell/armada/common/marvell_cci.c 5*91f16700Schasinglulu * 6*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 7*91f16700Schasinglulu * https://spdx.org/licenses 8*91f16700Schasinglulu */ 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <drivers/arm/cci.h> 11*91f16700Schasinglulu #include <lib/mmio.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <plat_marvell.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu static const int cci_map[] = { 16*91f16700Schasinglulu PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX, 17*91f16700Schasinglulu PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 18*91f16700Schasinglulu }; 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* 21*91f16700Schasinglulu * This redefines the weak definition in 22*91f16700Schasinglulu * plat/marvell/armada/common/marvell_cci.c 23*91f16700Schasinglulu */ 24*91f16700Schasinglulu void plat_marvell_interconnect_init(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu /* 27*91f16700Schasinglulu * To better utilize the address space, we remap CCI base address from 28*91f16700Schasinglulu * the default (0xD8000000) to MVEBU_CCI_BASE. 29*91f16700Schasinglulu * This has to be done here, rather than in cpu_wins_init(), because 30*91f16700Schasinglulu * cpu_wins_init() is called later. 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu mmio_write_32(CPU_DEC_CCI_BASE_REG, MVEBU_CCI_BASE >> 20); 33*91f16700Schasinglulu 34*91f16700Schasinglulu cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 35*91f16700Schasinglulu } 36