1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <common/bl_common.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <io_addr_dec.h> 11*91f16700Schasinglulu #include <mvebu_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu struct dec_win_config io_dec_win_conf[] = { 14*91f16700Schasinglulu /* dec_reg_base win_attr max_dram_win max_remap win_offset */ 15*91f16700Schasinglulu {0xc000, 0x3d, 2, 0, 0x08}, /* USB */ 16*91f16700Schasinglulu {0xc100, 0x3d, 3, 0, 0x10}, /* USB3 */ 17*91f16700Schasinglulu {0xc200, 0x3d, 2, 0, 0x10}, /* DMA */ 18*91f16700Schasinglulu {0xc300, 0x3d, 2, 0, 0x10}, /* NETA0 */ 19*91f16700Schasinglulu {0xc400, 0x3d, 2, 0, 0x10}, /* NETA1 */ 20*91f16700Schasinglulu {0xc500, 0x3d, 2, 0, 0x10}, /* PCIe */ 21*91f16700Schasinglulu {0xc800, 0x3d, 3, 0, 0x10}, /* SATA */ 22*91f16700Schasinglulu {0xca00, 0x3d, 3, 0, 0x08}, /* SD */ 23*91f16700Schasinglulu {0xcb00, 0x3d, 3, 0, 0x10}, /* eMMC */ 24*91f16700Schasinglulu {0xce00, 0x3d, 2, 0, 0x08}, /* EIP97 */ 25*91f16700Schasinglulu }; 26*91f16700Schasinglulu 27*91f16700Schasinglulu int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size) 28*91f16700Schasinglulu { 29*91f16700Schasinglulu *win = io_dec_win_conf; 30*91f16700Schasinglulu *size = sizeof(io_dec_win_conf)/sizeof(struct dec_win_config); 31*91f16700Schasinglulu 32*91f16700Schasinglulu return 0; 33*91f16700Schasinglulu } 34*91f16700Schasinglulu 35