1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef IO_ADDR_DEC_H 9*91f16700Schasinglulu #define IO_ADDR_DEC_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <stdint.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* There are 5 configurable cpu decoder windows. */ 14*91f16700Schasinglulu #define DRAM_WIN_MAP_NUM_MAX 5 15*91f16700Schasinglulu /* Target number for dram in cpu decoder windows. */ 16*91f16700Schasinglulu #define DRAM_CPU_DEC_TARGET_NUM 0 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* 19*91f16700Schasinglulu * Not all configurable decode windows could be used for dram, some units have 20*91f16700Schasinglulu * to reserve one decode window for other unit they have to communicate with; 21*91f16700Schasinglulu * for example, DMA engineer has 3 configurable windows, but only two could be 22*91f16700Schasinglulu * for dram while the last one has to be for pcie, so for DMA, its max_dram_win 23*91f16700Schasinglulu * is 2. 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu struct dec_win_config { 26*91f16700Schasinglulu uint32_t dec_reg_base; /* IO address decoder register base address */ 27*91f16700Schasinglulu uint32_t win_attr; /* IO address decoder windows attributes */ 28*91f16700Schasinglulu /* How many configurable dram decoder windows that this unit has; */ 29*91f16700Schasinglulu uint32_t max_dram_win; 30*91f16700Schasinglulu /* The decoder windows number including remapping that this unit has */ 31*91f16700Schasinglulu uint32_t max_remap; 32*91f16700Schasinglulu /* The offset between continuous decode windows 33*91f16700Schasinglulu * within the same unit, typically 0x10 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu uint32_t win_offset; 36*91f16700Schasinglulu }; 37*91f16700Schasinglulu 38*91f16700Schasinglulu struct dram_win { 39*91f16700Schasinglulu uintptr_t base_addr; 40*91f16700Schasinglulu uintptr_t win_size; 41*91f16700Schasinglulu }; 42*91f16700Schasinglulu 43*91f16700Schasinglulu struct dram_win_map { 44*91f16700Schasinglulu int dram_win_num; 45*91f16700Schasinglulu struct dram_win dram_windows[DRAM_WIN_MAP_NUM_MAX]; 46*91f16700Schasinglulu }; 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* 49*91f16700Schasinglulu * init_io_addr_dec 50*91f16700Schasinglulu * 51*91f16700Schasinglulu * This function initializes io address decoder windows by 52*91f16700Schasinglulu * cpu dram window mapping information 53*91f16700Schasinglulu * 54*91f16700Schasinglulu * @input: N/A 55*91f16700Schasinglulu * - dram_wins_map: cpu dram windows mapping 56*91f16700Schasinglulu * - io_dec_config: io address decoder windows configuration 57*91f16700Schasinglulu * - io_unit_num: io address decoder unit number 58*91f16700Schasinglulu * @output: N/A 59*91f16700Schasinglulu * 60*91f16700Schasinglulu * @return: 0 on success and others on failure 61*91f16700Schasinglulu */ 62*91f16700Schasinglulu int init_io_addr_dec(struct dram_win_map *dram_wins_map, 63*91f16700Schasinglulu struct dec_win_config *io_dec_config, 64*91f16700Schasinglulu uint32_t io_unit_num); 65*91f16700Schasinglulu 66*91f16700Schasinglulu #endif /* IO_ADDR_DEC_H */ 67