xref: /arm-trusted-firmware/plat/marvell/armada/a3k/common/include/ddr_info.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (C) 2018 Marvell International Ltd.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier:     BSD-3-Clause
5*91f16700Schasinglulu  * https://spdx.org/licenses
6*91f16700Schasinglulu  */
7*91f16700Schasinglulu 
8*91f16700Schasinglulu #ifndef DDR_INFO_H
9*91f16700Schasinglulu #define DDR_INFO_H
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #define DRAM_MAX_IFACE			1
12*91f16700Schasinglulu #define DRAM_CH0_MMAP_LOW_OFFSET	0x200
13*91f16700Schasinglulu 
14*91f16700Schasinglulu #endif /* DDR_INFO_H */
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