1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018 Marvell International Ltd. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu * https://spdx.org/licenses 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <armada_common.h> 11*91f16700Schasinglulu #include <dram_win.h> 12*91f16700Schasinglulu #include <io_addr_dec.h> 13*91f16700Schasinglulu #include <marvell_plat_priv.h> 14*91f16700Schasinglulu #include <plat_marvell.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* This routine does MPP initialization */ 17*91f16700Schasinglulu static void marvell_bl31_mpp_init(void) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu mmio_clrbits_32(MVEBU_NB_GPIO_SEL_REG, 1 << MVEBU_GPIO_TW1_GPIO_EN_OFF); 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* Set hidden GPIO setting for SPI. 22*91f16700Schasinglulu * In north_bridge_pin_out_en_high register 13804, 23*91f16700Schasinglulu * bit 28 is the one which enables CS, CLK pins to be 24*91f16700Schasinglulu * output, need to set it to 1. 25*91f16700Schasinglulu * The initial value of this bit is 1, but in UART boot mode 26*91f16700Schasinglulu * initialization, this bit is disabled and the SPI CS and CLK pins 27*91f16700Schasinglulu * are used for downloading image purpose; so after downloading, 28*91f16700Schasinglulu * we should set this bit to 1 again to enable SPI CS and CLK pins. 29*91f16700Schasinglulu * And anyway, this bit value should be 1 in all modes, 30*91f16700Schasinglulu * so here we does not judge boot mode and set this bit to 1 always. 31*91f16700Schasinglulu */ 32*91f16700Schasinglulu mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, 33*91f16700Schasinglulu 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); 34*91f16700Schasinglulu } 35*91f16700Schasinglulu 36*91f16700Schasinglulu /* This function overruns the same function in marvell_bl31_setup.c */ 37*91f16700Schasinglulu void bl31_plat_arch_setup(void) 38*91f16700Schasinglulu { 39*91f16700Schasinglulu struct dec_win_config *io_dec_map; 40*91f16700Schasinglulu uint32_t dec_win_num; 41*91f16700Schasinglulu struct dram_win_map dram_wins_map; 42*91f16700Schasinglulu 43*91f16700Schasinglulu marvell_bl31_plat_arch_setup(); 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* MPP init */ 46*91f16700Schasinglulu marvell_bl31_mpp_init(); 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* initialize the timer for delay functionality */ 49*91f16700Schasinglulu plat_delay_timer_init(); 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* CPU address decoder windows initialization. */ 52*91f16700Schasinglulu cpu_wins_init(); 53*91f16700Schasinglulu 54*91f16700Schasinglulu /* fetch CPU-DRAM window mapping information by reading 55*91f16700Schasinglulu * CPU-DRAM decode windows (only the enabled ones) 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu dram_win_map_build(&dram_wins_map); 58*91f16700Schasinglulu 59*91f16700Schasinglulu /* Get IO address decoder windows */ 60*91f16700Schasinglulu if (marvell_get_io_dec_win_conf(&io_dec_map, &dec_win_num)) { 61*91f16700Schasinglulu printf("No IO address decoder windows configurations found!\n"); 62*91f16700Schasinglulu return; 63*91f16700Schasinglulu } 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* IO address decoder init */ 66*91f16700Schasinglulu if (init_io_addr_dec(&dram_wins_map, io_dec_map, dec_win_num)) { 67*91f16700Schasinglulu printf("IO address decoder windows initialization failed!\n"); 68*91f16700Schasinglulu return; 69*91f16700Schasinglulu } 70*91f16700Schasinglulu } 71