1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu# Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 4*91f16700Schasinglulu# 5*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu# 7*91f16700Schasinglulu 8*91f16700SchasingluluPLAT_INCLUDES := \ 9*91f16700Schasinglulu -Iplat/intel/soc/stratix10/include/ \ 10*91f16700Schasinglulu -Iplat/intel/soc/common/drivers/ \ 11*91f16700Schasinglulu -Iplat/intel/soc/common/include/ 12*91f16700Schasinglulu 13*91f16700Schasinglulu# Include GICv2 driver files 14*91f16700Schasingluluinclude drivers/arm/gic/v2/gicv2.mk 15*91f16700SchasingluluAGX_GICv2_SOURCES := \ 16*91f16700Schasinglulu ${GICV2_SOURCES} \ 17*91f16700Schasinglulu plat/common/plat_gicv2.c 18*91f16700Schasinglulu 19*91f16700Schasinglulu 20*91f16700SchasingluluPLAT_BL_COMMON_SOURCES := \ 21*91f16700Schasinglulu ${AGX_GICv2_SOURCES} \ 22*91f16700Schasinglulu drivers/delay_timer/delay_timer.c \ 23*91f16700Schasinglulu drivers/delay_timer/generic_delay_timer.c \ 24*91f16700Schasinglulu drivers/ti/uart/aarch64/16550_console.S \ 25*91f16700Schasinglulu lib/xlat_tables/aarch64/xlat_tables.c \ 26*91f16700Schasinglulu lib/xlat_tables/xlat_tables_common.c \ 27*91f16700Schasinglulu plat/intel/soc/common/aarch64/platform_common.c \ 28*91f16700Schasinglulu plat/intel/soc/common/aarch64/plat_helpers.S \ 29*91f16700Schasinglulu plat/intel/soc/common/socfpga_delay_timer.c \ 30*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_firewall.c 31*91f16700Schasinglulu 32*91f16700SchasingluluBL2_SOURCES += \ 33*91f16700Schasinglulu common/desc_image_load.c \ 34*91f16700Schasinglulu drivers/mmc/mmc.c \ 35*91f16700Schasinglulu drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ 36*91f16700Schasinglulu drivers/io/io_storage.c \ 37*91f16700Schasinglulu drivers/io/io_block.c \ 38*91f16700Schasinglulu drivers/io/io_fip.c \ 39*91f16700Schasinglulu drivers/partition/partition.c \ 40*91f16700Schasinglulu drivers/partition/gpt.c \ 41*91f16700Schasinglulu drivers/synopsys/emmc/dw_mmc.c \ 42*91f16700Schasinglulu lib/cpus/aarch64/cortex_a53.S \ 43*91f16700Schasinglulu plat/intel/soc/stratix10/bl2_plat_setup.c \ 44*91f16700Schasinglulu plat/intel/soc/stratix10/soc/s10_clock_manager.c \ 45*91f16700Schasinglulu plat/intel/soc/stratix10/soc/s10_memory_controller.c \ 46*91f16700Schasinglulu plat/intel/soc/stratix10/soc/s10_mmc.c \ 47*91f16700Schasinglulu plat/intel/soc/stratix10/soc/s10_pinmux.c \ 48*91f16700Schasinglulu plat/intel/soc/common/bl2_plat_mem_params_desc.c \ 49*91f16700Schasinglulu plat/intel/soc/common/socfpga_image_load.c \ 50*91f16700Schasinglulu plat/intel/soc/common/socfpga_storage.c \ 51*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_emac.c \ 52*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_handoff.c \ 53*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_mailbox.c \ 54*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_reset_manager.c \ 55*91f16700Schasinglulu plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ 56*91f16700Schasinglulu plat/intel/soc/common/drivers/wdt/watchdog.c 57*91f16700Schasinglulu 58*91f16700Schasingluluinclude lib/zlib/zlib.mk 59*91f16700SchasingluluPLAT_INCLUDES += -Ilib/zlib 60*91f16700SchasingluluBL2_SOURCES += $(ZLIB_SOURCES) 61*91f16700Schasinglulu 62*91f16700SchasingluluBL31_SOURCES += \ 63*91f16700Schasinglulu drivers/arm/cci/cci.c \ 64*91f16700Schasinglulu lib/cpus/aarch64/aem_generic.S \ 65*91f16700Schasinglulu lib/cpus/aarch64/cortex_a53.S \ 66*91f16700Schasinglulu plat/common/plat_psci_common.c \ 67*91f16700Schasinglulu plat/intel/soc/stratix10/soc/s10_clock_manager.c \ 68*91f16700Schasinglulu plat/intel/soc/stratix10/bl31_plat_setup.c \ 69*91f16700Schasinglulu plat/intel/soc/common/socfpga_psci.c \ 70*91f16700Schasinglulu plat/intel/soc/common/socfpga_sip_svc.c \ 71*91f16700Schasinglulu plat/intel/soc/common/socfpga_sip_svc_v2.c \ 72*91f16700Schasinglulu plat/intel/soc/common/socfpga_topology.c \ 73*91f16700Schasinglulu plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 74*91f16700Schasinglulu plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 75*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_mailbox.c \ 76*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_reset_manager.c 77*91f16700Schasinglulu 78*91f16700SchasingluluPROGRAMMABLE_RESET_ADDRESS := 0 79*91f16700SchasingluluRESET_TO_BL2 := 1 80*91f16700SchasingluluUSE_COHERENT_MEM := 1 81