1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu 7*91f16700SchasingluluPLAT_INCLUDES := \ 8*91f16700Schasinglulu -Iplat/intel/soc/n5x/include/ \ 9*91f16700Schasinglulu -Iplat/intel/soc/common/drivers/ \ 10*91f16700Schasinglulu -Iplat/intel/soc/common/include/ 11*91f16700Schasinglulu 12*91f16700Schasinglulu# Include GICv2 driver files 13*91f16700Schasingluluinclude drivers/arm/gic/v2/gicv2.mk 14*91f16700SchasingluluDM_GICv2_SOURCES := \ 15*91f16700Schasinglulu ${GICV2_SOURCES} \ 16*91f16700Schasinglulu plat/common/plat_gicv2.c 17*91f16700Schasinglulu 18*91f16700Schasinglulu 19*91f16700SchasingluluPLAT_BL_COMMON_SOURCES := \ 20*91f16700Schasinglulu ${DM_GICv2_SOURCES} \ 21*91f16700Schasinglulu drivers/delay_timer/delay_timer.c \ 22*91f16700Schasinglulu drivers/delay_timer/generic_delay_timer.c \ 23*91f16700Schasinglulu drivers/ti/uart/aarch64/16550_console.S \ 24*91f16700Schasinglulu lib/xlat_tables/aarch64/xlat_tables.c \ 25*91f16700Schasinglulu lib/xlat_tables/xlat_tables_common.c \ 26*91f16700Schasinglulu plat/intel/soc/common/aarch64/platform_common.c \ 27*91f16700Schasinglulu plat/intel/soc/common/aarch64/plat_helpers.S \ 28*91f16700Schasinglulu plat/intel/soc/common/socfpga_delay_timer.c \ 29*91f16700Schasinglulu plat/intel/soc/common/drivers/ccu/ncore_ccu.c 30*91f16700Schasinglulu 31*91f16700SchasingluluBL2_SOURCES += 32*91f16700Schasinglulu 33*91f16700SchasingluluBL31_SOURCES += \ 34*91f16700Schasinglulu drivers/arm/cci/cci.c \ 35*91f16700Schasinglulu lib/cpus/aarch64/aem_generic.S \ 36*91f16700Schasinglulu lib/cpus/aarch64/cortex_a53.S \ 37*91f16700Schasinglulu plat/common/plat_psci_common.c \ 38*91f16700Schasinglulu plat/intel/soc/n5x/bl31_plat_setup.c \ 39*91f16700Schasinglulu plat/intel/soc/n5x/soc/n5x_clock_manager.c \ 40*91f16700Schasinglulu plat/intel/soc/common/socfpga_psci.c \ 41*91f16700Schasinglulu plat/intel/soc/common/socfpga_sip_svc.c \ 42*91f16700Schasinglulu plat/intel/soc/common/socfpga_sip_svc_v2.c \ 43*91f16700Schasinglulu plat/intel/soc/common/socfpga_topology.c \ 44*91f16700Schasinglulu plat/intel/soc/common/sip/socfpga_sip_ecc.c \ 45*91f16700Schasinglulu plat/intel/soc/common/sip/socfpga_sip_fcs.c \ 46*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_mailbox.c \ 47*91f16700Schasinglulu plat/intel/soc/common/soc/socfpga_reset_manager.c 48*91f16700Schasinglulu 49*91f16700SchasingluluPROGRAMMABLE_RESET_ADDRESS := 0 50*91f16700SchasingluluRESET_TO_BL2 := 1 51*91f16700SchasingluluBL2_INV_DCACHE := 0 52*91f16700SchasingluluUSE_COHERENT_MEM := 1 53