xref: /arm-trusted-firmware/plat/intel/soc/common/include/socfpga_vab.h (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #ifndef SOCFPGA_VAB_H
8*91f16700Schasinglulu #define SOCFPGA_VAB_H
9*91f16700Schasinglulu 
10*91f16700Schasinglulu 
11*91f16700Schasinglulu #include <stdlib.h>
12*91f16700Schasinglulu #include "socfpga_fcs.h"
13*91f16700Schasinglulu 
14*91f16700Schasinglulu struct fcs_hps_vab_certificate_data {
15*91f16700Schasinglulu 	uint32_t vab_cert_magic_num;			/* offset 0x10 */
16*91f16700Schasinglulu 	uint32_t flags;
17*91f16700Schasinglulu 	uint8_t rsvd0_1[8];
18*91f16700Schasinglulu 	uint8_t fcs_sha384[FCS_SHA384_WORD_SIZE];	/* offset 0x20 */
19*91f16700Schasinglulu };
20*91f16700Schasinglulu 
21*91f16700Schasinglulu struct fcs_hps_vab_certificate_header {
22*91f16700Schasinglulu 	uint32_t cert_magic_num;			/* offset 0 */
23*91f16700Schasinglulu 	uint32_t cert_data_sz;
24*91f16700Schasinglulu 	uint32_t cert_ver;
25*91f16700Schasinglulu 	uint32_t cert_type;
26*91f16700Schasinglulu 	struct fcs_hps_vab_certificate_data d;		/* offset 0x10 */
27*91f16700Schasinglulu 	/* keychain starts at offset 0x50 */
28*91f16700Schasinglulu };
29*91f16700Schasinglulu 
30*91f16700Schasinglulu /* Macros */
31*91f16700Schasinglulu #define IS_BYTE_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
32*91f16700Schasinglulu #define BYTE_ALIGN(x, a)		__ALIGN_MASK((x), (typeof(x))(a)-1)
33*91f16700Schasinglulu #define __ALIGN_MASK(x, mask)		(((x)+(mask))&~(mask))
34*91f16700Schasinglulu #define VAB_CERT_HEADER_SIZE		sizeof(struct fcs_hps_vab_certificate_header)
35*91f16700Schasinglulu #define VAB_CERT_MAGIC_OFFSET		offsetof(struct fcs_hps_vab_certificate_header, d)
36*91f16700Schasinglulu #define VAB_CERT_FIT_SHA384_OFFSET	offsetof(struct fcs_hps_vab_certificate_data, fcs_sha384[0])
37*91f16700Schasinglulu #define SDM_CERT_MAGIC_NUM		0x25D04E7F
38*91f16700Schasinglulu #define CHUNKSZ_PER_WD_RESET		(256 * 1024)
39*91f16700Schasinglulu 
40*91f16700Schasinglulu /* SHA related return Macro */
41*91f16700Schasinglulu #define ENOVABIMG		1 /* VAB certificate not available */
42*91f16700Schasinglulu #define EIMGERR		2 /* Image format/size not valid */
43*91f16700Schasinglulu #define ETIMEOUT		3 /* Execution timeout */
44*91f16700Schasinglulu #define EPROCESS		4 /* Process error */
45*91f16700Schasinglulu #define EKEYREJECTED		5/* Key was rejected by service */
46*91f16700Schasinglulu 
47*91f16700Schasinglulu /* Function Definitions */
48*91f16700Schasinglulu static size_t get_img_size(uint8_t *img_buf, size_t img_buf_sz);
49*91f16700Schasinglulu int socfpga_vendor_authentication(void **p_image, size_t *p_size);
50*91f16700Schasinglulu static uint32_t get_unaligned_le32(const void *p);
51*91f16700Schasinglulu void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
52*91f16700Schasinglulu unsigned char *output, unsigned int chunk_sz);
53*91f16700Schasinglulu 
54*91f16700Schasinglulu #endif
55