1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SOCFPGA_PRIVATE_H 8*91f16700Schasinglulu #define SOCFPGA_PRIVATE_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include "socfpga_plat_def.h" 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define EMMC_DESC_SIZE (1<<20) 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define EMMC_INIT_PARAMS(base, clk) \ 15*91f16700Schasinglulu { .bus_width = MMC_BUS_WIDTH_4, \ 16*91f16700Schasinglulu .clk_rate = (clk), \ 17*91f16700Schasinglulu .desc_base = (base), \ 18*91f16700Schasinglulu .desc_size = EMMC_DESC_SIZE, \ 19*91f16700Schasinglulu .flags = 0, \ 20*91f16700Schasinglulu .reg_base = SOCFPGA_MMC_REG_BASE \ 21*91f16700Schasinglulu } 22*91f16700Schasinglulu 23*91f16700Schasinglulu typedef enum { 24*91f16700Schasinglulu BOOT_SOURCE_FPGA = 0, 25*91f16700Schasinglulu BOOT_SOURCE_SDMMC, 26*91f16700Schasinglulu BOOT_SOURCE_NAND, 27*91f16700Schasinglulu BOOT_SOURCE_RSVD, 28*91f16700Schasinglulu BOOT_SOURCE_QSPI 29*91f16700Schasinglulu } boot_source_type; 30*91f16700Schasinglulu 31*91f16700Schasinglulu /******************************************************************************* 32*91f16700Schasinglulu * Function and variable prototypes 33*91f16700Schasinglulu ******************************************************************************/ 34*91f16700Schasinglulu 35*91f16700Schasinglulu void enable_nonsecure_access(void); 36*91f16700Schasinglulu 37*91f16700Schasinglulu void socfpga_io_setup(int boot_source); 38*91f16700Schasinglulu 39*91f16700Schasinglulu void socfgpa_configure_mmu_el3(unsigned long total_base, 40*91f16700Schasinglulu unsigned long total_size, 41*91f16700Schasinglulu unsigned long ro_start, 42*91f16700Schasinglulu unsigned long ro_limit, 43*91f16700Schasinglulu unsigned long coh_start, 44*91f16700Schasinglulu unsigned long coh_limit); 45*91f16700Schasinglulu 46*91f16700Schasinglulu 47*91f16700Schasinglulu void socfpga_configure_mmu_el1(unsigned long total_base, 48*91f16700Schasinglulu unsigned long total_size, 49*91f16700Schasinglulu unsigned long ro_start, 50*91f16700Schasinglulu unsigned long ro_limit, 51*91f16700Schasinglulu unsigned long coh_start, 52*91f16700Schasinglulu unsigned long coh_limit); 53*91f16700Schasinglulu 54*91f16700Schasinglulu void socfpga_delay_timer_init(void); 55*91f16700Schasinglulu 56*91f16700Schasinglulu void socfpga_gic_driver_init(void); 57*91f16700Schasinglulu 58*91f16700Schasinglulu void socfpga_delay_timer_init_args(void); 59*91f16700Schasinglulu 60*91f16700Schasinglulu uint32_t socfpga_get_spsr_for_bl32_entry(void); 61*91f16700Schasinglulu 62*91f16700Schasinglulu uint32_t socfpga_get_spsr_for_bl33_entry(void); 63*91f16700Schasinglulu 64*91f16700Schasinglulu unsigned long socfpga_get_ns_image_entrypoint(void); 65*91f16700Schasinglulu 66*91f16700Schasinglulu void plat_secondary_cpus_bl31_entry(void); 67*91f16700Schasinglulu 68*91f16700Schasinglulu #endif /* SOCFPGA_PRIVATE_H */ 69