1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SOCFPGA_EMAC_H 8*91f16700Schasinglulu #define SOCFPGA_EMAC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* EMAC PHY Mode */ 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define PHY_INTERFACE_MODE_GMII_MII 0 13*91f16700Schasinglulu #define PHY_INTERFACE_MODE_RGMII 1 14*91f16700Schasinglulu #define PHY_INTERFACE_MODE_RMII 2 15*91f16700Schasinglulu #define PHY_INTERFACE_MODE_RESET 3 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* Mask Definitions */ 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define PHY_INTF_SEL_MSK 0x3 20*91f16700Schasinglulu #define FPGAINTF_EN_3_EMAC_MSK(x) (1 << (x * 8)) 21*91f16700Schasinglulu 22*91f16700Schasinglulu void socfpga_emac_init(void); 23*91f16700Schasinglulu 24*91f16700Schasinglulu #endif /* SOCFPGA_EMAC_H */ 25