1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <lib/mmio.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include "watchdog.h" 11*91f16700Schasinglulu 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* Reset watchdog timer */ 14*91f16700Schasinglulu void watchdog_sw_rst(void) 15*91f16700Schasinglulu { 16*91f16700Schasinglulu mmio_write_32(WDT_CRR, WDT_SW_RST); 17*91f16700Schasinglulu } 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* Print component information */ 20*91f16700Schasinglulu void watchdog_info(void) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu INFO("Component Type : %x\r\n", mmio_read_32(WDT_COMP_VERSION)); 23*91f16700Schasinglulu INFO("Component Version : %x\r\n", mmio_read_32(WDT_COMP_TYPE)); 24*91f16700Schasinglulu } 25*91f16700Schasinglulu 26*91f16700Schasinglulu /* Check watchdog current status */ 27*91f16700Schasinglulu void watchdog_status(void) 28*91f16700Schasinglulu { 29*91f16700Schasinglulu if (mmio_read_32(WDT_CR) & 1) { 30*91f16700Schasinglulu INFO("Watchdog Timer is currently enabled\n"); 31*91f16700Schasinglulu INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR)); 32*91f16700Schasinglulu } else { 33*91f16700Schasinglulu INFO("Watchdog Timer is currently disabled\n"); 34*91f16700Schasinglulu } 35*91f16700Schasinglulu } 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* Initialize & enable watchdog */ 38*91f16700Schasinglulu void watchdog_init(int watchdog_clk) 39*91f16700Schasinglulu { 40*91f16700Schasinglulu uint8_t cycles_i = 0; 41*91f16700Schasinglulu uint32_t wdt_cycles = WDT_MIN_CYCLES; 42*91f16700Schasinglulu uint32_t top_init_cycles = WDT_PERIOD * watchdog_clk; 43*91f16700Schasinglulu 44*91f16700Schasinglulu while ((cycles_i < 15) && (wdt_cycles < top_init_cycles)) { 45*91f16700Schasinglulu wdt_cycles = (wdt_cycles << 1); 46*91f16700Schasinglulu cycles_i++; 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i); 50*91f16700Schasinglulu 51*91f16700Schasinglulu mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN); 52*91f16700Schasinglulu } 53