1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <errno.h> 9*91f16700Schasinglulu #include <stdbool.h> 10*91f16700Schasinglulu #include <string.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <arch_helpers.h> 13*91f16700Schasinglulu #include <common/debug.h> 14*91f16700Schasinglulu #include <drivers/cadence/cdns_nand.h> 15*91f16700Schasinglulu #include <drivers/delay_timer.h> 16*91f16700Schasinglulu #include <lib/mmio.h> 17*91f16700Schasinglulu #include <lib/utils.h> 18*91f16700Schasinglulu #include "nand.h" 19*91f16700Schasinglulu 20*91f16700Schasinglulu #include "agilex5_pinmux.h" 21*91f16700Schasinglulu #include "combophy/combophy.h" 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* Pinmux configuration */ 24*91f16700Schasinglulu static void nand_pinmux_config(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN0SEL), SOCFPGA_PINMUX_SEL_NAND); 27*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN1SEL), SOCFPGA_PINMUX_SEL_NAND); 28*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN2SEL), SOCFPGA_PINMUX_SEL_NAND); 29*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN3SEL), SOCFPGA_PINMUX_SEL_NAND); 30*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN4SEL), SOCFPGA_PINMUX_SEL_NAND); 31*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN5SEL), SOCFPGA_PINMUX_SEL_NAND); 32*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN6SEL), SOCFPGA_PINMUX_SEL_NAND); 33*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN7SEL), SOCFPGA_PINMUX_SEL_NAND); 34*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN8SEL), SOCFPGA_PINMUX_SEL_NAND); 35*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN9SEL), SOCFPGA_PINMUX_SEL_NAND); 36*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN10SEL), SOCFPGA_PINMUX_SEL_NAND); 37*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN11SEL), SOCFPGA_PINMUX_SEL_NAND); 38*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN12SEL), SOCFPGA_PINMUX_SEL_NAND); 39*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN13SEL), SOCFPGA_PINMUX_SEL_NAND); 40*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN14SEL), SOCFPGA_PINMUX_SEL_NAND); 41*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN16SEL), SOCFPGA_PINMUX_SEL_NAND); 42*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN17SEL), SOCFPGA_PINMUX_SEL_NAND); 43*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN18SEL), SOCFPGA_PINMUX_SEL_NAND); 44*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN19SEL), SOCFPGA_PINMUX_SEL_NAND); 45*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN20SEL), SOCFPGA_PINMUX_SEL_NAND); 46*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN21SEL), SOCFPGA_PINMUX_SEL_NAND); 47*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN22SEL), SOCFPGA_PINMUX_SEL_NAND); 48*91f16700Schasinglulu mmio_write_32(SOCFPGA_PINMUX(PIN23SEL), SOCFPGA_PINMUX_SEL_NAND); 49*91f16700Schasinglulu } 50*91f16700Schasinglulu 51*91f16700Schasinglulu int nand_init(handoff *hoff_ptr) 52*91f16700Schasinglulu { 53*91f16700Schasinglulu /* NAND pin mux configuration */ 54*91f16700Schasinglulu nand_pinmux_config(); 55*91f16700Schasinglulu 56*91f16700Schasinglulu return cdns_nand_host_init(); 57*91f16700Schasinglulu } 58