1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu #include <errno.h> 9*91f16700Schasinglulu #include <stdbool.h> 10*91f16700Schasinglulu #include <string.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <arch_helpers.h> 13*91f16700Schasinglulu #include <common/debug.h> 14*91f16700Schasinglulu #include <drivers/cadence/cdns_sdmmc.h> 15*91f16700Schasinglulu #include <drivers/delay_timer.h> 16*91f16700Schasinglulu #include <lib/mmio.h> 17*91f16700Schasinglulu #include <lib/utils.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu #include "combophy.h" 20*91f16700Schasinglulu #include "sdmmc/sdmmc.h" 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* Temp assigned handoff data, need to remove when SDM up and run. */ 23*91f16700Schasinglulu void config_nand(handoff *hoff_ptr) 24*91f16700Schasinglulu { 25*91f16700Schasinglulu /* This is hardcoded input value for Combo PHY and SD host controller. */ 26*91f16700Schasinglulu hoff_ptr->peripheral_pwr_gate_array = 0x40; 27*91f16700Schasinglulu 28*91f16700Schasinglulu } 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* DFI configuration */ 31*91f16700Schasinglulu int dfi_select(handoff *hoff_ptr) 32*91f16700Schasinglulu { 33*91f16700Schasinglulu uint32_t data = 0; 34*91f16700Schasinglulu 35*91f16700Schasinglulu /* Temp assigned handoff data, need to remove when SDM up and run. */ 36*91f16700Schasinglulu handoff reverse_handoff_ptr; 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* Temp assigned handoff data, need to remove when SDM up and run. */ 39*91f16700Schasinglulu config_nand(&reverse_handoff_ptr); 40*91f16700Schasinglulu 41*91f16700Schasinglulu if (((reverse_handoff_ptr.peripheral_pwr_gate_array) & PERIPHERAL_SDMMC_MASK) == 0U) { 42*91f16700Schasinglulu ERROR("SDMMC/NAND is not set properly\n"); 43*91f16700Schasinglulu return -ENXIO; 44*91f16700Schasinglulu } 45*91f16700Schasinglulu 46*91f16700Schasinglulu mmio_setbits_32(SOCFPGA_SYSMGR(DFI_INTF), 47*91f16700Schasinglulu (((reverse_handoff_ptr.peripheral_pwr_gate_array) & 48*91f16700Schasinglulu PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)); 49*91f16700Schasinglulu data = mmio_read_32(SOCFPGA_SYSMGR(DFI_INTF)); 50*91f16700Schasinglulu if ((data & DFI_INTF_MASK) != (((reverse_handoff_ptr.peripheral_pwr_gate_array) & 51*91f16700Schasinglulu PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)) { 52*91f16700Schasinglulu ERROR("DFI is not set properly\n"); 53*91f16700Schasinglulu return -ENXIO; 54*91f16700Schasinglulu } 55*91f16700Schasinglulu 56*91f16700Schasinglulu return 0; 57*91f16700Schasinglulu } 58*91f16700Schasinglulu 59*91f16700Schasinglulu int combo_phy_init(handoff *hoff_ptr) 60*91f16700Schasinglulu { 61*91f16700Schasinglulu /* SDMMC/NAND DFI selection based on system manager DFI register */ 62*91f16700Schasinglulu int ret = dfi_select(hoff_ptr); 63*91f16700Schasinglulu 64*91f16700Schasinglulu if (ret != 0U) { 65*91f16700Schasinglulu ERROR("DFI configuration failed\n"); 66*91f16700Schasinglulu return ret; 67*91f16700Schasinglulu } 68*91f16700Schasinglulu 69*91f16700Schasinglulu return 0; 70*91f16700Schasinglulu } 71