1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch.h> 8*91f16700Schasinglulu #include <arch_helpers.h> 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu #include <plat/common/platform.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include "socfpga_private.h" 13*91f16700Schasinglulu 14*91f16700Schasinglulu 15*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 16*91f16700Schasinglulu { 17*91f16700Schasinglulu return PLAT_SYS_COUNTER_FREQ_IN_TICKS; 18*91f16700Schasinglulu } 19*91f16700Schasinglulu 20*91f16700Schasinglulu unsigned long socfpga_get_ns_image_entrypoint(void) 21*91f16700Schasinglulu { 22*91f16700Schasinglulu return PLAT_NS_IMAGE_OFFSET; 23*91f16700Schasinglulu } 24*91f16700Schasinglulu 25*91f16700Schasinglulu /****************************************************************************** 26*91f16700Schasinglulu * Gets SPSR for BL32 entry 27*91f16700Schasinglulu *****************************************************************************/ 28*91f16700Schasinglulu uint32_t socfpga_get_spsr_for_bl32_entry(void) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu /* 31*91f16700Schasinglulu * The Secure Payload Dispatcher service is responsible for 32*91f16700Schasinglulu * setting the SPSR prior to entry into the BL32 image. 33*91f16700Schasinglulu */ 34*91f16700Schasinglulu return 0; 35*91f16700Schasinglulu } 36*91f16700Schasinglulu 37*91f16700Schasinglulu /****************************************************************************** 38*91f16700Schasinglulu * Gets SPSR for BL33 entry 39*91f16700Schasinglulu *****************************************************************************/ 40*91f16700Schasinglulu uint32_t socfpga_get_spsr_for_bl33_entry(void) 41*91f16700Schasinglulu { 42*91f16700Schasinglulu unsigned long el_status; 43*91f16700Schasinglulu unsigned int mode; 44*91f16700Schasinglulu uint32_t spsr; 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* Figure out what mode we enter the non-secure world in */ 47*91f16700Schasinglulu el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 48*91f16700Schasinglulu el_status &= ID_AA64PFR0_ELX_MASK; 49*91f16700Schasinglulu 50*91f16700Schasinglulu mode = (el_status) ? MODE_EL2 : MODE_EL1; 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* 53*91f16700Schasinglulu * TODO: Consider the possibility of specifying the SPSR in 54*91f16700Schasinglulu * the FIP ToC and allowing the platform to have a say as 55*91f16700Schasinglulu * well. 56*91f16700Schasinglulu */ 57*91f16700Schasinglulu spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 58*91f16700Schasinglulu return spsr; 59*91f16700Schasinglulu } 60*91f16700Schasinglulu 61