1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4*91f16700Schasinglulu * 5*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 6*91f16700Schasinglulu */ 7*91f16700Schasinglulu 8*91f16700Schasinglulu #ifndef PLAT_SOCFPGA_DEF_H 9*91f16700Schasinglulu #define PLAT_SOCFPGA_DEF_H 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include "agilex_system_manager.h" 12*91f16700Schasinglulu #include <platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* Platform Setting */ 15*91f16700Schasinglulu #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX 16*91f16700Schasinglulu #define BOOT_SOURCE BOOT_SOURCE_SDMMC 17*91f16700Schasinglulu #define PLAT_PRIMARY_CPU 0 18*91f16700Schasinglulu #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 19*91f16700Schasinglulu #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* FPGA config helpers */ 22*91f16700Schasinglulu #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 23*91f16700Schasinglulu #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* QSPI Setting */ 26*91f16700Schasinglulu #define CAD_QSPIDATA_OFST 0xff900000 27*91f16700Schasinglulu #define CAD_QSPI_OFFSET 0xff8d2000 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* Register Mapping */ 30*91f16700Schasinglulu #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 31*91f16700Schasinglulu #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define SOCFPGA_MMC_REG_BASE 0xff808000 34*91f16700Schasinglulu #define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 35*91f16700Schasinglulu #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 36*91f16700Schasinglulu #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 37*91f16700Schasinglulu 38*91f16700Schasinglulu #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 39*91f16700Schasinglulu #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 40*91f16700Schasinglulu #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 41*91f16700Schasinglulu #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 42*91f16700Schasinglulu 43*91f16700Schasinglulu /******************************************************************************* 44*91f16700Schasinglulu * Platform memory map related constants 45*91f16700Schasinglulu ******************************************************************************/ 46*91f16700Schasinglulu #define DRAM_BASE (0x0) 47*91f16700Schasinglulu #define DRAM_SIZE (0x80000000) 48*91f16700Schasinglulu 49*91f16700Schasinglulu #define OCRAM_BASE (0xFFE00000) 50*91f16700Schasinglulu #define OCRAM_SIZE (0x00040000) 51*91f16700Schasinglulu 52*91f16700Schasinglulu #define MEM64_BASE (0x0100000000) 53*91f16700Schasinglulu #define MEM64_SIZE (0x1F00000000) 54*91f16700Schasinglulu 55*91f16700Schasinglulu #define DEVICE1_BASE (0x80000000) 56*91f16700Schasinglulu #define DEVICE1_SIZE (0x60000000) 57*91f16700Schasinglulu 58*91f16700Schasinglulu #define DEVICE2_BASE (0xF7000000) 59*91f16700Schasinglulu #define DEVICE2_SIZE (0x08E00000) 60*91f16700Schasinglulu 61*91f16700Schasinglulu #define DEVICE3_BASE (0xFFFC0000) 62*91f16700Schasinglulu #define DEVICE3_SIZE (0x00008000) 63*91f16700Schasinglulu 64*91f16700Schasinglulu #define DEVICE4_BASE (0x2000000000) 65*91f16700Schasinglulu #define DEVICE4_SIZE (0x0100000000) 66*91f16700Schasinglulu 67*91f16700Schasinglulu #define BL2_BASE (0xffe00000) 68*91f16700Schasinglulu #define BL2_LIMIT (0xffe1b000) 69*91f16700Schasinglulu 70*91f16700Schasinglulu #define BL31_BASE (0x1000) 71*91f16700Schasinglulu #define BL31_LIMIT (0x81000) 72*91f16700Schasinglulu 73*91f16700Schasinglulu /******************************************************************************* 74*91f16700Schasinglulu * UART related constants 75*91f16700Schasinglulu ******************************************************************************/ 76*91f16700Schasinglulu #define PLAT_UART0_BASE (0xFFC02000) 77*91f16700Schasinglulu #define PLAT_UART1_BASE (0xFFC02100) 78*91f16700Schasinglulu 79*91f16700Schasinglulu /******************************************************************************* 80*91f16700Schasinglulu * GIC related constants 81*91f16700Schasinglulu ******************************************************************************/ 82*91f16700Schasinglulu #define PLAT_GIC_BASE (0xFFFC0000) 83*91f16700Schasinglulu #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) 84*91f16700Schasinglulu #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) 85*91f16700Schasinglulu #define PLAT_GICR_BASE 0 86*91f16700Schasinglulu 87*91f16700Schasinglulu #define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) 88*91f16700Schasinglulu #define PLAT_HZ_CONVERT_TO_MHZ (1000000) 89*91f16700Schasinglulu 90*91f16700Schasinglulu /******************************************************************************* 91*91f16700Schasinglulu * SDMMC related pointer function 92*91f16700Schasinglulu ******************************************************************************/ 93*91f16700Schasinglulu #define SDMMC_READ_BLOCKS mmc_read_blocks 94*91f16700Schasinglulu #define SDMMC_WRITE_BLOCKS mmc_write_blocks 95*91f16700Schasinglulu 96*91f16700Schasinglulu /******************************************************************************* 97*91f16700Schasinglulu * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 98*91f16700Schasinglulu * is done and HPS should trigger warm reset via RMR_EL3. 99*91f16700Schasinglulu ******************************************************************************/ 100*91f16700Schasinglulu #define L2_RESET_DONE_REG 0xFFD12218 101*91f16700Schasinglulu 102*91f16700Schasinglulu /* Platform specific system counter */ 103*91f16700Schasinglulu #define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk() 104*91f16700Schasinglulu 105*91f16700Schasinglulu #endif /* PLAT_SOCFPGA_DEF_H */ 106